Imagination Technologies Limited

Nordic Semiconductor Asa

Adrian John Anderson

Paul Murrin

Mohammed El-Hajjar

Gary Christopher Wass

Gareth J Davies

Christopher Owen

Peter Bagnall

David William Knox

Michael John Davis

Martin John Woodhead

Taku Yamagata

Matthew Gilbert

Henry Liu

Matt Gilbert

Paul Damon Murrin

Gareth John Davies

Steven Meade

Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.

Tile based interleaving and de-interleaving for digital signal processing

A GNSS receiver comprises a memory interface and a vector processor. The vector processor is configured to: receive, via the memory interface, an array comprising a plurality of correlation results stored in a memory, each correlation result associated with a respective combination of possible receiver parameters for the GNSS receiver; process the array to identify a subset of the correlation results in the array; and retain, in the memory, the identified subset and discard, from the memory, those correlation results of the plurality of correlation results not in the identified subset.

GNSS receiver candidate selection

A technique for efficient calling of functions on a processor generates an executable program having a function call by analysing an interface for the function that defines an argument expression and an internal value used solely within the function, and an argument declaration defining an argument value to be provided to the function when the program is run. A data structure is generated including the internal value and a resolved argument value derived from the argument expression and the argument value. A single instruction is encoded in the program to utilise the data structure. When the program is executed on a processor, the single instruction causes the processor to load the argument value and internal value from the data structure into registers in the processor, prior to evaluating the function. The function can then be executed without further register loads being performed.

Function evaluation using multiple values loaded into registers by a single instruction

Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P(where P&#x2265;P) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than P*q bits.

Decoder for low-density parity-check codes

A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

Digital signal processing data transfer

A gaussian frequency shift keying (GFSK) detector comprising a multi-symbol detector; at least three Viterbi decoders, and a timing adjustment module. The multi-symbol detector receives a series of samples representing a received GFSK modulated signal which comprises at least three samples per symbol; and generates, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, at least three sets of soft decisions values, each set of soft decision values indicating the probability that the N-symbol sequence of samples is each possible N-symbol pattern based on a different one of the at least three samples of a symbol being a centre sample of the symbol. Each Viterbi decoder generates, for each N-symbol sequence, a path metric for each possible N-symbol pattern from a different set of soft decision values according to a Viterbi decoding algorithm. The timing adjustment module generates a timing adjustment signal based on the path metrics generated by the Viterbi decoders to adjust the sample timing.

Systems and methods for adjusting the sample timing of a GFSK modulated signal

A GNSS correlator comprises a buffer and a processing unit. The buffer is configured to store input data representing sample values of a GNSS signal captured over a pre-defined time window. The processing unit is configured to receive one or more correlation parameters in a control signal, and, in a first pass, read the input data from the buffer and perform a first correlation operation on the input data, and, in a second pass, re-read the same input data from the buffer and perform a second correlation operation on the same input data, wherein the second correlation operation is different to the first correlation operation.

GNSS correlator

A ranging code correlation function detection system for use in a global navigation satellite system (GNSS) receiver includes a correlation block to correlate a digitized GNSS signal (e.g. at or above a critical sampling rate) with a corresponding ranging code at each of a plurality of different offsets from a current estimate of a code delay to generate a plurality of correlation data points; an interpolation filter configured to generate at least one estimated correlation data point that lies between two of the correlation data points based on the current estimate of the code delay. In some cases the ranging code correlation function detection system may also include a discriminator block configured to generate an updated estimate of the code delay based on the at least one estimated correlation data point.

Efficient detection of ranging code correlation function of a GNSS signal

A Gaussian frequency shift keying (GFSK) detector for decoding a GFSK signal. The detector includes: a multi-symbol detector and a Viterbi decoder. The multi-symbol detector is configured to: receive a series of samples representing a received GFSK modulated signal; and generate, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, a plurality of soft decision values that indicate the probability that the N-symbol sequence is each possible N-symbol pattern, wherein N is an integer greater than or equal to two. The Viterbi decoder is configured to estimate each N-symbol sequence using a Viterbi decoding algorithm wherein the soft decision values for the N-symbol sequence are used as branch metrics in the Viterbi decoding algorithm.

GFSK detector

An IQ amplitude balance estimator is described herein which uses a positive frequency mixer to generate two outputs. The first output is the standard output from a positive frequency mixer and the second output corresponds to a spectrum inverted output from a negative frequency mixer. The second output is generated, however, using the same partial products as the first output and no negative frequency mixer is used. An IQ amplitude imbalance metric is generated by taking the real part of the output from correlation logic which performs a correlation of the two outputs from the mixer. This metric may then be used in a closed loop to compensate for any IQ amplitude imbalance.

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Chepstow, United Kingdom

Adrian John Anderson