Ati Technologies Inc.

Ati International Srl

Adrian H Hartog

Milivoje M Aleksic

Chun Wang

Raymond M Li

Sanford S Lum

Daniel Gudmundson

Oleg Drapkin

Gordon Caruk

Carl K Mizuyabu

Grigory Temkine

Michael A Alford

Robert P Bicevskis

Fridtjof Martin Weigel

Indra Laksono

Hugh Chow

John S Kitamura

Jerzy Kielbasinski

Robin E Davies

Fridtjof Martin Georg Weigel

Josh Grossman

Dan O Gudmundson

A method and apparatus for graphics rendered in a mobile device includes a command queue capable of receiving a plurality of rendering commands, a generate_event command and a wait_until command. The wait_until command corresponds to the completion of a specific operation indicated by the generate_event command. The method and apparatus further includes a direct memory access device operably coupled to the command queue, wherein the DMA device is capable of receiving a memory access command in response to the generate_event command. A memory device is capable of storing rendering information, wherein the memory device is accessible in response to the generate_event command. Furthermore, the method and apparatus includes the command queue capable of queuing the rendering commands in response to the wait_until command until the completion of the operation indicated by the generate_event command.

Method and apparatus for graphics rendering on a mobile device

A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.

Display FIFO memory management system

A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M commands per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data at a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four-times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.

Method and apparatus for accessing memory

A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M command per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.

System for accessing memory and method therefore

A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other suitable functions. A multiplexer, configured as a time slicer, selects data for transfer with the memory over a first bus at a first rate. The multichannel serializer is coupled between the multiplexer and a plurality of controllers through a plurality of second buses. Each of the second buses is associated with a different channel. The multichannel serializer has a serializer for each of the plurality of second buses wherein each of the serializers transfers data associated with a channel at a second rate associated with a corresponding controller.

Serialized mapped memory configuration for a video graphics chip

A method of providing text data for display in a processor controlled apparatus comprised of storing data defining a text character in a memory, in packed monochrome bit map form, addressing the memory to read the text character data, providing the text character to a graphics processor circuit, performing a bitblt operation on each bit of the text character while providing a color attribute, and storing the packed text character having a color attribute for subsequent display.

Text optimization

A method and apparatus for processing video data at various optimum operating rates is accomplished by a video graphics circuit that includes a video graphics module, a buffer and a memory interface, where the video graphics module, which may be a graphical user interface (GUI), is operated at a first clock rate and the memory interface is operated at a second clock rate. In this circuit, the buffer temporarily stores data, such that communications with the memory interface are done at the second clock rate while communications with the video graphics module are done at the fist clock rate.

Method and apparatus for processing video graphics information at different operating rates

A multiple pipeline memory controller has a plurality of two stage pipeline processors dedicated to separately process real time video capture and display refresh input request signals. A separate pipeline processor processes non-real time input signals. The multiple pipeline design reduces memory access latency and improves throughput of data in display FIFO memory to effect improved resolution. The multiple pipeline memory controller can be integrated in a video graphics controller (VGC).

Multiple pipeline memory controller for servicing real time data

A method of addressing a computer subsystem memory comprised of establishing an aperture having a predetermined page size, addressing the memory at address boundaries defining multiples of half the page size, and reading or writing a page of data from or to the subsystem memory using the established aperture at consecutive memory locations beginning at one of the boundaries.

Page address space with varying page size and boundaries

A method of performing a bit block transfer (Bitblt) comprised of reading a pixel data sequence from a source trajectory, writing an X coordinate portion of the pixel data sequence to a destination trajectory, repeating the writing step to the end of a scan line in the event the X coordinate portion is smaller than the scan line, reset the X coordinate following the end of the scan line, reset a Y coordinate and write a successive X coordinate portion of the pixel data sequence to the destination register from an X coordinate start position when the Y coordinate actually advances in the pixel data sequence.

General pattern blit source type

A computer system is comprised of at least one of a main bus and an attached expansion bus, a CPU connected to the main bus, peripherals connected to one of the main bus or to the expansion buses, a subsystem connected to a bus for receiving control, address and data signals from the CPU comprising a graphics controller, a data compression circuit, a video controller, a memory connected to data input ports of the circuits and controllers via a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, a first arbiter for determining which controller is permitted access the memory, a link bus connecting each of the controllers, and apparatus for providing polling signals to each of the controllers and circuits on the link bus and for receiving acknowledgement signals therefrom, and thereby synchronizing and allowing exchange of control information between the controllers and circuits.

Multi-media computer architecture

A method of drawing moving images on a graphics display comprising (a) receiving data defining an input image in a predetermined resolution, (b) commanding a graphics processor to draw a corresponding image frame on a display having a number of scanning lines which is a multiple m of a number of scanning lines of the input image and a multiple n of a number of pixels in a horizontal line of the input image, (c) drawing successive lines of the input image on a first and on each m.sup.th scanning line of the graphics display, while stretching each pixel on each drawn line over n pixels, (d) copying each drawn line on respective immediately following m-1 lines, and (e) repeating steps (b)-(d) for successive frames of the input image.

Accelerated full screen video playback

A method for drawing lines on a graphics device in such manner in that only those points lying inside a specified rectangular area of the device are drawn. Predetermined digital outcodes are generated for defining the endpoints of the lines and a decision is made whether to draw or not draw the lines based on the relationship of the endpoints with respect to both the specified rectangular area of the device, and a second larger rectangular area of the device.

Growing community of inventors

Toronto, Canada

Adrian H Hartog