Intel Corporation

International Business Machines Corporation

Adrian C Moga

Herbert H Hum

Yen-Cheng Liu

Eric J DeHaemer

Vedaraman Geetha

Eric R Delano

James R Vash

Leena K Puthiyedath

Brinda Ganesh

Ganesh Kumar

Richard Lawrence Carlson

David Bubien

Scott J Erlanger

Michelle M Sebot

Ren Wang

Zeshan A Chishti

Aamer Jaleel

Malcolm Mandviwalla

Christopher J Hughes

Glenn J Hinton

Rajesh M Sankaran

Tsung-Yuan Charles Tai

Robert G Blankenship

Christian Maciocco

Andrew J Herdrich

Alexander W Min

Jr-Shian Tsai

Jong Soo Park

Ronak Singhal

Mesut A Ergin

Jeffrey D Chamberlain

Namakkal N Venkatesan

Thomas Benjamin Berg

Dale Beyer

Shubhendu Sekhar Mukherjee

Raj K Ramanujan

Sreenivas Subramoney

Avinash Sodani

Ankush Varma

Rajat Agarwal

Wilfred Gomes

Deborah T Marr

David Zimmerman

Lihu Rappoport

Robert S Chappell

Stephen R Van Doren

Sailesh Kottapalli

Bahaa Fahim

Donald R DeSota

Rajesh S Parthasarathy

Anant V Nori

Vincent Edward Von Bokern

Muthukumar Swaminathan

John G Holm

Arijit Biswas

Sebastien Hily

Bongjin Jung

Eric R DeLano

Wayne Alan Downer

Ramya Jayaram Masti

Madhavan Parthasarathy

Larry O Smith

Niranjan K Soundararajan

Abhishek Sharma

Carl E Love

Liqun Cheng

Steven E Raasch

Russell M Clapp

Hanna Alam

Prathmesh Kallurkar

Scott J Cape

Thomas Toll

Niranjan Kumar Soundararajan

Wayne A Downer

Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.

De-prioritizing speculative code lines in on-chip caches

In one embodiment, an apparatus includes a memory and a scheduler. The scheduler is coupled to the memory and a memory controller. The memory stores a plurality of metadata requests. Each of the plurality of metadata requests is associated with one of a plurality of metadata priority levels. The scheduler schedules transmission of a first metadata request of the plurality of metadata requests to the memory controller based at least in part on a first metadata priority level associated with the first metadata request and a first bandwidth portion of a metadata request bandwidth. The first bandwidth portion is associated with the first metadata priority level. Other embodiments are described and claimed.

System, apparatus, and method for scheduling metadata requests

Three-dimensional (3D) DRAM integrated in the same package as compute logic enable forming high-density caches. In one example, an integrated 3D DRAM includes a large on-de cache (such as a level 4 (L4) cache), a large on-die memory-side cache, or both an L4 cache and a memory-side cache. One or more tag caches cache recently accessed tags from the L4 cache, the memory-side cache, or both. A cache controller in the compute logic is to receive a request from one of the processor cores to access an address and compare tags in the tag cache with the address. In response to a hit in the tag cache, the cache controller accesses data from the cache at a location indicated by an entry in the tag cache, without performing a tag lookup in the cache.

Integrated three-dimensional (3D) DRAM cache

Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

Processor and method implementing a cacheline demote machine instruction

Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads

A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Processors having virtually clustered cores and cache slices

In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.

Virtual shared cache mechanism in a processing device

An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M') state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.

Cache coherency apparatus and method minimizing memory writeback operations

A processor may include a memory controller to interface with a system memory having a near memory and a far memory. The processor may include logic circuitry to cause memory controller to determine whether a write request is generated remotely or locally, and when the write request is generated remotely to instruct the memory controller to perform a read of near memory before performing a write, when the write request is generated locally and a cache line targeted by the write request is in the inclusive state to instruct the memory controller to perform the write without performing a read of near memory, and when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state to instruct the memory controller to read near memory before performing the write.

Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory

In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.

Obtaining data for redundant multithreading (RMT) execution

An apparatus is described that includes a plurality of processors, a plurality of cache slices and respective cache agents. Each of the cache agents have a buffer to store requests from the processors. The apparatus also includes a network between the processors and the cache slices to carry traffic of transactions that invoke the processors and/or said cache agents. The apparatus also includes communication resources between the processors and the cache agents reserved to transport one or more warnings from one or more of the cache agents to the processors that the one or more cache agents' respective buffers have reached a storage capacity threshold.

Multi-processor computing system having fast processor response to cache agent request capacity limit warning

In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

Apparatus, method, and system for implementing micro page tables

Growing community of inventors

Portland, OR, United States of America

Adrian C Moga