Burr-brown Corporation

Adrian B Early

William J Lillis

A latch circuit utilizes a series-gated, emitter coupled logic structure including a current source providing a gate current substantially proportional to temperature for developing an output signal swing substantially proportional to temperature, thereby allowing the output signal swing to have a reduced magnitude at nominal temperatures. The load across which the output signal is developed includes a resistor coupled in series with a semiconductor P-N junction. Emitter areas of emitter-coupled transistor pairs within the latch circuit are mismatched for creating an offset tending to compensate changes in the voltage across the semiconductor junction within the load resulting from the switching action of the latch circuit. A bias circuit maintains the switching threshold reference voltage substantially intermediate the output signal swing. The semiconductor junction within the load of the latch circuit may correspond with the base-emitter junction of a transistor, and an additional load resistor may be coupled to the collector thereof for providing a second output signal swing of increased magnitude isolated from the feedback path of the latch circuit. In an alternate embodiment, the semiconductor junction within the load is eliminated, and a follower transistor is inserted within the feedback path of the latch circuit for level-shifting the output signal voltage developed across the load resistor and providing a low impedance source thereof.

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Tucson, AZ, United States of America

Adrian B Early