Rockwell Collins, Inc.

Adrian A Hill

Lee M Paulsen

Dana J Jensen

Thomas B Campbell

Bryan S McCoy

Michael C Meholensky

Anders P Walker

Roger A Dana

Vadim Olen

Connor C McBryde

James B West

Daniel L Woodell

Russell David Wyse

Michael L Hageman

Jeremiah Damien Wolf

Paul L Opsahl

Joel T Gillett

Systems and apparatuses include an electronically scanned array system including a power supply system, a radiating element subarray, a plurality of beamformer chips, and a plurality of control buses. The radiating element subarray includes active radiating elements, and between about one percent and about twenty percent reserve radiating elements distributed throughout the active radiating elements. Each control bus includes a plurality of primary control paths providing communication from the control bus to the beamformer chips, and a reserve control paths structured to be remapped to provide communication from the control bus to the beam former chips in the event that one of the plurality of primary control paths fails.

Electronically scanned array

An antenna array testing circuit can include a circuitry including a plurality of memory registers, a testing sequence generation logic, and a testing control logic. The memory registers can store, for each antenna element of a plurality of antenna elements of the phased antenna array, a corresponding antenna element ID. The memory registers can store a testing step ID indicative of a testing step of a sequence of testing steps. The testing sequence generation logic can determine, for each antenna element of the phased antenna array, using the corresponding antenna element ID and the testing step ID, a corresponding testing signal indicative of a testing state of the antenna element during the testing step. The testing control logic can cause each antenna element the phased antenna array to be configured according to the corresponding testing signal during the testing step.

Embedded antenna array metrology systems and methods

Systems and methods relate to an electronically scanned antenna array. A beamforming circuit includes a first input, a first output, a second input, a second output and an antenna interface. The antenna interface is coupled to the electronically scanned antenna array. A first control circuit is coupled to the first input and the first output and is configured to provide first beamforming data to the beamforming circuit via the first input. A second control circuit is coupled to the second input and the second output and is configured to provide second beamforming data to the beam forming circuit via the second input.

Control architecture for electronically scanned array

Systems and apparatuses include an electronically scanned array system including a power supply system, a radiating element subarray, a plurality of beamformer chips, and a plurality of control buses. The power supply system a first power converter structured to receive and condition mains power, a second power converter arranged in parallel with the first power converter, and a controller structured to monitor the first power converter and the second power converter and to operate one of a first switch or a second switch to provide conditioned power. The radiating element subarray includes active radiating elements, and between about one percent and about twenty percent reserve radiating elements distributed throughout the active radiating elements. Each control bus includes a plurality of primary control paths providing communication from the control bus to the beamformer chips, and a reserve control paths structured to be remapped to provide communication from the control bus to the beam former chips in the event that one of the plurality of primary control paths fails.

Methods and Systems for testing phased antenna arrays include positioning a phased antenna array and a probe antenna at relative positions with respect to each other where one of them can operate as the transmitter and the other as the receiver. The transmitter can radiate a plurality of electromagnetic waves sequentially while the phased antenna array is steered or configured differently for each radiated electromagnetic. The receiver can receive, responsive to each radiated electromagnetic wave, a corresponding receive radio frequency (RF) signal. A processor can determine one or more performance parameters of the phased antenna array using the receive RF signals.

Methods and systems for ESA metrology

An Electronically Scanned Array (ESA) antenna is controlled via an optical domain without electrical conductors on the ESA Printed Wiring Board (PWB). Distribution of the control signal occurs over pulses of light through an optical medium separate from the ESA PWB. External to the ESA PWB are one or more optical wave guides functional as communications channels which connect the ESA optical receivers/transceivers with transmitters/transceivers interfaced to a system controller. The ESA is divided into groups of elements with serial busses and discrete signals driven by local controllers. The local controller for each group of elements may include one or more optical receivers (unidirectional) or transceivers (bidirectional). This concept offers a trade in electrical complexity associated with an ESA PWB for an additional manufactured medium redundantly supplying the control signal to the ESA as well as routing the RF data signal from the ESA to the system controller.

Optically controlled electronically scanned array

Electronically scanned arrays and multi-chip modules (MCMs) that may be used in such arrays are provided. One MCM may include a set of one or more first semiconductor components and a plurality of second semiconductor components. The first semiconductor component set is coupled to the plurality of second semiconductor components, and the first semiconductor component set is configured to control the plurality of second semiconductor components. Each of the plurality of second semiconductor components is accessible through a plurality of data strings providing communication between the first semiconductor component set and the plurality of second semiconductor components, each data string defining a unique path between the first semiconductor component set and the plurality of second semiconductor components, such that the plurality of data strings provide redundant data paths between the first semiconductor component set and the plurality of second semiconductor components.

Multi-chip module architecture

A timer for measuring a time lapsed during an acceleration is disclosed. The timer may include a piezoelectric sensor, an energy storage device and a measurement module. The piezoelectric sensor includes a piezoelectric material for generating an electric potential in response to the acceleration. The energy storage device is electrically coupled to the piezoelectric sensor and is configured for receiving the electric potential generated by the piezoelectric sensor. The measurement module is electrically coupled to the energy storage device. The measurement module measures the electric potential received at the energy storage device and determines the time lapsed during the acceleration based on the electric potential received at the energy storage device.

Piezoelectric acceleration timer

Disclosed are control systems, and more specifically control systems which benefit from a long-gate time for measurement and a rapid sample time to enhance responsiveness and methods and systems for utilizing multiple-staggered, overlapping gates where the gate time is an integer multiple of the time between ends of adjacent gates. The system continuously counts at the wavefronts or zero-crossings of a frequency reference signal and temporarily records them in registers and compares the contents of registers separated by a gate time and outputs a sample after every sample time.

Growing community of inventors

Vinton, IA, United States of America

Adrian A Hill