Freescale Semiconductor,inc.

Motorola Corporation

Adolfo C Reyes

Darrell Glenn Hill

Ernest Schirmann

Julio C Costa

Marino J Martinez

Agni Mitra

Karthik Rajagopalan

Ronghua Zhu

Vishnu Khemka

Tahir Arif Khan

Stephen J Cosentino

Eric Shanks Johnson

Mark R Wilson

William C Peatman

An LDMOSFET transistor () is provided which includes a substrate (), an epitaxial drift region () in which a drain region () is formed, a first well region () in which a source region () is formed, a gate electrode () formed adjacent to the source region () to define a first channel region (), and a grounded substrate injection suppression guard structure that includes a patterned buried layer () in ohmic contact with an isolation well region () formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region () and from the drain region (), where the buried layer () is disposed below the first well region () but not below the drain region ().

Guard ring integrated LDMOS

Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.

ESD protection for passive integrated devices

A method of manufacturing a semiconductor component includes providing a substrate ( ) with a surface ( ), providing a layer ( ) of undoped gallium arsenide over the surface of the substrate, forming a gate contact ( ) over a first portion of the layer, and removing a second portion of the layer.

Method of manufacturing a semiconductor component and semiconductor component thereof

A semiconductor device includes a transistor (30, 51) having a gate electrode (15, 52) wherein the gate electrode (15, 52) has a highly resistive portion (24, 25, 55). The highly resistive portion (24, 25, 55) is integrated into the gate electrode (15, 52) and is coupled to the gate electrode (15, 52) using a via-less contact method.

Semiconductor transistor with stabilizing gate electrode

A semiconductor device (20) is formed on a compound semiconductor substrate (21). The semiconductor device (20) is oriented on the surface (40) of the compound semiconductor substrate (21) such that the physical forces that result from the thermal heating or cooling of the compound semiconductor substrate (21) are essentially equal. This orientation reduces the variability of the drain to source current of the semiconductor device (20) as the semiconductor device (20) is operated at different temperatures.

Compound semiconductor device having reduced temperature variability

Growing community of inventors

Tempe, AZ, United States of America

Adolfo C Reyes