Ii-vi Delaware, Inc.

Ii-vi Advanced Materials, LLC

Acreo Ab

Ascatron Ab

Adolf Schöner

Sergey Reshanov

Hossein Elahipanah

Nicolas Thierry-Jebali

Christian Vieider

Wlodzimierz Kaplan

There is provided a method for manufacturing a SiC device wafer comprising the steps: a) slicing and polishing a SiC boule to thicker substrates compared to the usual thickness in the prior art, b) creating a device wafer on the substrate, c) removing the device wafer from the remaining substrate, d) adding SiC to the remaining substrate so that the original thickness of the substrate is essentially restored, and repeating steps b)-d). The removal of the device wafer can be made for instance by laser slicing. Advantages include that the SiC material loss is significantly decreased and the boule material used for device wafers is considerably increased, the substrates become more stable especially during high temperature processes, the warp and bow is reduced, the risk of breakage is decreased.

Crystal efficient SiC device wafer production

A grid is manufactured with a combination of ion implant and epitaxy growth. The grid structure is made in a SiC semiconductor material with the steps of a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer (n), b) by epitaxial growth adding at least one doped semiconductor SiC material to form separated second regions (p) on the first layer (n), if necessary with aid of removing parts of the added semiconductor material to form separated second regions (p) on the first layer (n), and c) by ion implantation at least once at a stage selected from the group consisting of directly after step a), and directly after step b); implanting ions in the first layer (n) to form first regions (p). It is possible to manufacture a grid with rounded corners as well as an upper part with a high doping level. It is possible to manufacture a component with efficient voltage blocking, high current conduction, low total resistance, high surge current capability, and fast switching.

Method for manufacturing a grid

A modular concept for Silicon Carbide power devices is disclosed where a low voltage module (LVM) is designed separately from a high voltage module (HVM). The LVM having a repeating structure in at least a first direction, the repeating structure repeats with a regular distance in at least the first direction, the HVM comprising a buried grid () with a repeating structure in at least a second direction, the repeating structure repeats with a regular distance in at least the second direction, along any possible defined direction. Advantages include faster easier design and manufacture at a lower cost.

Concept for silicon carbide power devices

There is disclosed the integration of a Schottky diode with a MOSFET, more in detail there is a free-wheeling Schottky diode and a power MOSFET on top of a buried grid material structure. Advantages of the specific design allow the whole surface area to be used for MOSFET and Schottky diode structures, the shared drift layer is not limited by Schottky diode or MOSFET design rules and therefore, one can decrease the thickness and increase the doping concentration of the drift layer closer to a punch through design compared to the state of the art. This results in higher conductivity and lower on-resistance of the device with no influence on the voltage blocking performance. The integrated device can operate at higher frequency. The risk for bipolar degradation is avoided.

Integration of a Schottky diode with a MOSFET

There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions comprising an access region and a JFET region defining the length of the MOS channel, and wherein the access region and the JFET region are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel is defined by simultaneous creating n-type regions on both sides of the channel using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.

MOSFET in SiC with self-aligned lateral MOS channel

A feeder design is manufactured as a structure in a SiC semiconductor material comprising at least two p-type grids in an n-type SiC material (), comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material () wherein the at least two p-type grids () are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material () between the first and a second regions without any grids.

Feeder design with high current capability

Concept for silicon for carbide power devices

A feeder design is manufactured as a structure in a SIC semiconductor material comprising at least two p-type grids in an n-type SiC material (), comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material () wherein the at least two p-type grids () are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material () between the first and a second regions without any grids.

There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions () comprising an access region () and a JFET region () defining the length of the MOS channel (), and wherein the access region () and the JFET region () are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel () is defined by simultaneous creating n-type regions on both sides of the channel () using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.

MOSFET in sic with self-aligned lateral MOS channel

A modular concept for Silicon Carbide power devices is disclosed where a low voltage module (LVM) is designed separately from a high voltage module (HVM). The LVM having a repeating structure in at least a first direction, the repeating structure repeats with a regular distance in at least the first direction, the HVM comprising a buried grid with a repeating structure in at least a second direction, the repeating structure repeats with a regular distance in at least the second direction, along any possible defined direction. Advantages include faster easier design and manufacture at a lower cost.

A feeder design is manufactured as a structure in a SiC semiconductor material comprising at least two p-type grids in an n-type SiC material, comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material wherein the at least two p-type grids are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material between the first and a second regions without any grids.

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Hässelby, Sweden

Adolf Schöner