Intel Corporation

Aditya Sreenivas

Peter L Doyle

Kim A Meinerth

Krishnan Sreenivas

Thomas A Piazza

Todd M Witter

Josh B Mastronarde

Tuong P Trieu

Zohar Bogin

Wishwesh Anil Gandhi

Anoop Mukker

David E Freker

Alankar Saxena

John A Carey

Tom A Piazza

Joydeep Ray

Altug Koker

Prasoonkumar Surti

David J Harriman

Michael Mantor

David Wyatt

Jasmin Ajanovic

Blaise B Fanning

David M Puffer

Bryan R White

Trung Am Diep

Steve John Clohset

Robert N Murdoch

Jeffrey L Rabe

Russell W Dyer

Marc D Torrant

Kam Leung

Stuart E Sailer

Brian D Rauchfuss

Jonathan B Sadowsky

Timothy M Dobbins

Adam H Wilen

Marcus Grindstaff

Sam W Jensen

Sajjad A Zaidi

Neil Schaper

R Scott Hartog

Surti B Prasoonkumar

A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

Isochronous agent data pinning in a multi-level memory system

Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Optimized memory addressing

An image is rendered by dividing the image into chunks, rendering the chunks in one of at least two devices, and determining which of the devices renders each one of at least some of the chunks based on at least one device's progress in the rendering of other chunks.

Image rendering

An apparatus and method are disclosed for synchronization of command processing from multiple command queues. Various embodiments employ a condition code register that indicates which queues should have processing suspended until a specified event condition occurs. Upon satisfaction of the specified condition, processing of commands from the suspended queue is resumed.

Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device

A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context manager stores in a first memory area and restores from the first memory area information describing a first rendering context associated with a first independent image. The graphics context manager stores in a second memory area and restores from the second memory area information describing a second rendering context associated with a second independent image.

Apparatus, method and system with a graphics-rendering engine having a graphics context manager

A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.

Apparatus, method and system with a graphics-rendering engine having a time allocator

A method and apparatus for managing overlay data requests are disclosed. One embodiment of an apparatus includes a request unit and a timer. A request is made by a graphics controller to the request unit for a line of overlay data. The request unit divides the request from the graphics controller into a series of smaller requests. The smaller requests are issued to a memory controller. Delays are inserted between each of the smaller requests in order to allow other system resources to more easily gain access to memory.

Efficient management of memory access requests from a video data stream

A method, system, and apparatus to reduce power consumption of a memory by actively asserting the CKE pin based at least in part on a LRU status of the rows in an active mode.

Method, system, and apparatus for reducing power consumption of a memory

Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

Memory arbiter with intelligent page gathering logic

Memory arbiter with grace and ceiling periods and intelligent page gathering logic

Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.

Dual memory channel interleaving for graphics and video

The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.

Automatic memory management

A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.

Depth write disable for rendering

Growing community of inventors

El Dorado Hills, CA, United States of America

Aditya Sreenivas