Intel Corporation

Other

Aditya Navale

Altug Koker

Murali Ramadoss

Balaji Vembu

Hema Chand Nalluri

Eric C Samson

Ankur N Shah

David M Puffer

Jeffery S Boles

Saurabh Sharma

Bryan R White

Subramaniam M Maiyuran

Prasoonkumar Surti

Joydeep Ray

Michael Apodaca

Ben J Ashbaugh

James A Valerio

Wishwesh Anil Gandhi

Jorge F Garcia Pabon

Travis T Schluessler

Peter L Doyle

Brandon L Fliflet

Jonathan B Sadowsky

Abhishek R Appu

Mahesh S Natu

Justin Decell

Ronald W Silvas

Sudheendra Srivathsa

Raghavendra Kamath Miyar

Vasanth Ranganathan

Rajesh M Sankaran

Aravindh V Anantaraman

Abhishek Venkatesh

Pattabhiraman K

Chandra S Gurram

Vikranth Vemulapalli

Leslie E Cline

Vidhya Krishnan

Vamsee Vardhan Chivukula

Jonathan B Sadowski

Gilbert A Neiger

David Wyatt

David I Poisner

Andrew V Anderson

Scott R Janus

Changliang Wang

Zohar Bogin

James B Crossland

Philip R Lantz

Larry D Seiler

Niranjan L Cooray

Asit K Mallick

William A Stevens, Jr

David J Cowperthwaite

Karol A Szerszen

Arthur Hunter, Jr

Satish K Damaraju

Anoop Mukker

Todd M Witter

Sathyamurthi Sadhasivan

Michael K Dwyer

Ariel Berkovits

Tuong P Trieu

Anirban Kundu

Naveen Matam

Siripong Sritanyaratana

Ying Cui

Joseph Koston

Win Sheng Cheng

David I Standring

Brian D Rauchfuss

Richard W Jensen

Joseph W Tsang

Lalit K Saptarshi

Kritika Bala

Sandeep S Sodhi

Shailesh Shah

Mark A Blake

Brian E Ruttenberg

Arthur D Hunter Jr

Sreekanth Mavila

Vijay R Sar-Dessai

Hema Chand Nallluri

Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.

Local memory translation table accessed and dirty flags

A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.

Unified stateless compression system for universally consumable compression

An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.

Tile sequencing mechanism

Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

Apparatus and method for scalable error detection and reporting

Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

Systems and methods in a graphics environment for providing shared virtual memory addressing support for a host system

An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.

Asynchronous execution mechanism

Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

Workload scheduling and distribution on a distributed graphics device

An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.

Interconnected systems fence mechanism

An apparatus to facilitate memory flushing is disclosed. The apparatus comprises a cache memory, one or more processing resources, tracker hardware to dispatch workloads for execution at the processing resources and to monitor the workloads to track completion of the execution, range based flush (RBF) hardware to process RBF commands and generate a flush indication to flush data from the cache memory and a flush controller to receive the flush indication and perform a flush operation to discard data from the cache memory at an address range provided in the flush indication.

Range based flushing mechanism

In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

System, apparatus and method for multi-die distributed memory mapped input/output support

Growing community of inventors

Folsom, CA, United States of America

Aditya Navale