Freescale Semiconductor,inc.

Nxp Usa, Inc.

Aditya Musunuri

Amol V Bhinge

Kumar Abhishek

Yi Zheng

Subhashrahul Shekhar

A system-on-chip (SoC) having a switchable power domain capable of being placed in a standby mode during which a power supply of the switchable power domain is gated and having an always-on power domain. The always-on power domain includes an input sampling circuit, and the switchable power domain includes an input/output (IO) circuit configured to, during normal operation, receive data at a corresponding signal pin when an input buffer of the IO circuit is enabled, in which the corresponding signal pin is coupled to the input sampling circuit. The input sampling circuit is configured to, while the switchable power domain is entering the standby mode but before the power supply is gated, provide an override input enable signal to enable the input buffer of the IO circuit, sample an input bit value on the corresponding signal pin, and store the sampled bit value to provide an injection current fault indicator.

Fault detection during entry to or exit from low power mode

Provided are a system and method for generating final result checking for a test case. A test case is executed for a coherent memory system having a processor core. An event log is generated for the processor core. The event log is analyzed. The test case for the core is annotated with a checker for performing expected data checking for physical addresses modified by the processor core.

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Austin, TX, United States of America

Aditya Musunuri