International Business Machines Corporation

Aditya Kumar

Ahmed Gheith

Kevin James Wendzel

Curtis Shannon Eide

Ronald Lynn Rockhold

Tracy James Bashore

Andrew R Malota

Alwood Patrick Williams, Iii

Andrew James Declercq

Michael T Kalmbach

Andrew J Geissler

Marc Dickenson

Adriana Kobylak

Timothy L Thompson

Brent Robert Tiefenthaler

Steven E Vaughan

Bradley J Vette

A method utilizes event-driven reoptimization to reallocate one or more logical partitions within a pool of logically-partitioned data processing systems in a logically-partitioned computing environment in response to detection of a system event that is likely to increase or decrease the collective resource demands of logical partitions resident in a logically-partitioned computing environment. The reoptimization may be used to consolidate logical partitions on fewer processor nodes to improve the potential for powering down hardware resources and thereby reduce power consumption.

Event-driven reoptimization of logically-partitioned environment for power management

A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.

Memory frame proxy architecture for synchronization and check handling in a simulator

Simulation method using memory frame proxy architecture for synchronization and check handling

The invention addresses these and other problems associated with the prior art by providing an apparatus and program product that utilize event-driven reoptimization to reallocate one or more logical partitions within a pool of logically-partitioned data processing systems in response to detection of a system event that is likely to increase or decrease the collective resource demands of logical partitions resident in a logically-partitioned computing environment. In some instances, for example, the reoptimization may be used to consolidate logical partitions on fewer processor nodes to improve the potential for powering down hardware resources and thereby reduce power consumption.

A simulation technique that handles accesses to a frame of instruction memory by inserting a command object between a frame proxy and a memory frame provides improved throughput in simulation environments. The instruction frame, if present, processes the access to the frame. If an instruction frame is not present for the accessed frame, the memory frame handles the request directly. The instruction frame caches fetched and decoded instructions and may be inserted at the first access to a corresponding instruction memory frame. The instruction frame can track write accesses to instruction memory so that changes to the instruction memory can be reflected in the state of the instruction frame. Additional check frames may be chained between the interface and the memory frame to handle breakpoints, instruction memory watches or other access checks on the instruction memory frame.

Memory frame architecture for instruction fetches in simulation

A mechanism is provided for handling interrupt actions for inter-thread communication. In association with a first processor thread, a thread action data structure is provided that comprises a non-blocking synchronization data structure and an internal list data structure of pending interrupts having no form of synchronization. A post of an interrupt action is received from a second processor thread to the thread action data structure associated with the first processor thread, where the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure. The interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread. The internal list data structure of pending interrupts is processed to thereby handle interrupt actions moved to the internal list data structure.

Handling interrupt actions for inter-thread communication

Techniques are described for managing states of an object using a finite-state machine. The states may be used to indicate whether an object has been added, removed, requested or updated. Embodiments of the invention generally include dividing a process into at least two threads where a first thread changes the state of the object while the second thread performs the processing of the data found in the object. While the second thread is processing the data, the first thread may receive additional updates and change the states of the objects to inform the second thread that it should process the additional updates when the second thread becomes idle.

Handling and reporting of object state transitions on a multiprocess architecture

Performance impact of a computing system component on a transient end-to-end system operation is estimated by profiling an overall characteristic for a transient end-to-end system operation, and simultaneously profiling a program code component for a second characteristic, thereby collecting a first pair of data points, repeating the operational period while introducing a known artificial delay into the program code component, and while profiling the overall performance characteristic for the system and for the program code component, thereby collecting pairs of data points for each repetition of the operational period for each of the artificial delays; curve fitting and analyzing intercepts of the collected data points to estimate the effect of the artificial delays in the program code component on the transient end-to-end system operation; and reporting the estimate correlated to potential optimal transient end-to-end system operation.

Indirect software performance analysis

Method, apparatus and system are described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system.

Conversion of timestamps between multiple entities within a computing system

Method is described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system.

Growing community of inventors

Austin, TX, United States of America

Aditya Kumar