Intel Corporation

Aditya Kasukurti

Biswajeet Guha

William Hsu

Jun Sung Kang

Erica J Thompson

Kai Loon Cheong

Jack T Kavalieros

Matthew V Metz

Ian A Young

Tanay Gosavi

Seung Hoon Sung

Uygar E Avci

Chia-Ching Lin

Ashish Verma Penumatcha

Bruce E Beattie

Sou-Chi Chang

Owen Y Loh

A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

Nanowire transistor structure and method of shaping

Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

Transistor device with (anti)ferroelectric spacer structures

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Hillsboro, OR, United States of America

Aditya Kasukurti