Cadence Design Systems, Inc.

Aditya Chandra

Nikhil Gupta

Shilpa Gandotra

Inderpal Singh

Ishani Jain

Gunjan Goel

A planned schematic for an electronic system is hierarchically divided into base-level schematic blocks which may be designed individually. In accordance with a plurality of sets of design requirements, variant overlays are designed for each base-level schematic block, each overlay including variant parameter values which may replace corresponding parameter values of the schematic blocks. The schematic blocks are integrated to generate a system-level schematic, and the variant overlays for a given set of design requirements are merged to generate a system variant overlay. Parameter values of the system variant overlay may then replace corresponding parameter values of the system-level schematic to generate a variant schematic for the given set of design requirements. Using this system and methodology, variant designs may be collaboratively generated by multiple designers each with expertise in particular schematic blocks and/or variant requirements, and may be shared either at the system level or at lower levels.

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Delhi, India

Aditya Chandra