Nvidia Corporation

Adithya Hrudhayan Krishnamurthy

Ish Chadha

A system includes a link having one or more data paths and a device coupled with the link and including a data link (DL) transmitter and a buffer. The device is to write one or more bits corresponding to a operation to a first portion of a data frame in response to an indication, the data frame comprising a second portion comprising data. The device is to transmit the first portion and the second portion of the data frame via the one or more data paths in response to writing the one or more bits corresponding to the operation. The device is to store the data frame at the buffer in response to writing the one or more bits corresponding to the operation.

Method and system for transmitting in-band cross-chip triggers to maintain high-speed interconnect

A receiver device includes detection logic, error counter logic, and threshold logic. The detection detects frame errors in data frames received by a transmitter device. The error counter logic increments a first value of an error count responsive to each error signal, indicative of a frame error in a data frame, received from the detection logic. The error counter logic reduces the first value to a second value (non-zero value) for the error count responsive to receiving a decrement signal and a period marker signal corresponding to a programmable period. The error counter logic resets the first value or the second value of the error count to zero responsive to receiving a reset signal. The threshold logic compares a current value of the error count with a threshold number of frame errors and output an interrupt responsive to the current value satisfying the threshold number of frame errors.

Error rate interrupts in hardware for high-speed signaling interconnect

A receiver device includes detection logic, an error counter, and an interrupt logic. The detection logic is to receive a first set of data frames and detect one or more frame errors in the first set of data frames. The error counter is to store a number of the one or more frame errors detected in the first set of data frames. The interrupt logic can be coupled to the error counter. The interrupt logic is to specify a period and compare the number of the one or more frame errors with a threshold number of frame errors during the period, where the interrupt logic is to indicate an interrupt responsive to the number of the one or more frame errors detected within the period satisfying the threshold number of frame errors.

A system includes a first device and a second device coupled to a link. The first device is to transmit one or more request frames for synchronization of a data layer, each request frame including a quantity of bits and an error code. The second device is to receive a first set of bits corresponding to the quantity of bits in each request frame. The second device is to perform an error decode operation on the first set of bits using a first portion of the first set of bits and determine the first set of bits correspond to a frame boundary of the one more request frames responsive to a success of the error decode operation. The second device is to transmit an acknowledgement of the synchronization of the data layer based on determining the first set of bits corresponds to the frame boundary.

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Sunnyvale, CA, United States of America

Adithya Hrudhayan Krishnamurthy