Qualcomm Incorporated

Adithya Bhaskaran

Mukund Narasimhan

Shiba Narayan Mohanty

Sharad Kumar Gupta

Sei Seung Yoon

Rahul Sahu

Pradeep Raj

Veerabhadra Rao Boda

Akshdeepika

A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

Memory with high-speed and area-efficient read path

A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.

Low-power and high-density core-power lowering for memory write assist

A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.

SRAM write yield enhancement with pull-up strength modulation

A dual-power-domain SRAM is disclosed in which the dual power domains may be powered up or down in whatever order is desired. For example, a (CX) power domain may be powered up first, followed by a memory (MX) power domain. Conversely, the MX power domain may be powered up prior to the CX domain.

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Chennai, India

Adithya Bhaskaran