Intel Corporation

Adit D Tarmaster

Michael N Derr

David I Poisner

Mikal Hunsaker

Zohar Bogin

Joseph A Bennett

Darren L Abramson

Anoop Mukker

William Knolla

Amir Zinaty

Haim Lustig

According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.

Mechanism for a shared serial peripheral interface

Embodiments of the present invention provide a method and apparatus for detecting an interruption in memory initialization. A status bit for indicating whether memory initialization was interrupted or not is stored in a register. A basic input/output system (BIOS) sets the status bit prior to initialization and clears the status bit after initialization. The status bit cannot be reset by a standard platform reset. In operation, as the system is reset or turned on and prior to initialization, the BIOS checks the status bit to detect possible improper memory initialization. When the status bit is set, the BIOS concludes that a memory initialization had not completed and thus might be incorrect. The BIOS then causes power to be cycled to memory and any other steps needed are taken to return the memory to a functional state.

Method and apparatus for detecting an interruption in memory initialization

The present invention is in the field of bridging transactions from one bus to a second bus. More particularly, embodiments of the present invention can enhance an interface between two buses by ordering split-completion transactions to one or more hosts.

Data bridge and bridging

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Citrus Heights, CA, United States of America

Adit D Tarmaster