Texas Instruments Corporation

Hitachi, Ltd.

Hitachi Ltd, of Japan

Adin E Hyslop

Charvaka Duvvury

Takesada Akiba

Masayuki Nakamura

Jimmie D Childers

Hiroshi Otori

Hugh Pryor McAdams

Goro Kitsukawa

Wah Kit Loh

Akitoshi Nishimura

Danny R Cline

Daniel A Baudouin

Mark A Kressley

Jeffrey W Janzen

Hideo Sunami

Chok Y Hung

A semiconductor device is disclosed. The device includes an integrated circuit chip having integral de-coupling capacitors on the chip backside. The de-coupling capacitors includes a metal layer in intimate contact with the semiconductor substrate of the integrated circuit, a dielectric layer and a second metal layer. The second metal layer is segmented to form multiple capacitors, and each capacitor is interconnected to power supplies of the chip. Interconnection to different integrated circuit packages is provided. A method of making the semiconductor device is also disclosed.

Integrated capacitor on the back of a chip

An apparatus and method for a logic circuit that advantageously adapts to different operating voltages. In a preferred embodiment, a logic circuit of the present invention is implemented to drive a large capacitive load and includes a first driver, comprising a set of small, low-current drive transistors, a second driver, comprising a set of large, high-speed transistors, and an additional transistor connected between the two drivers. The additional transistor can be selectively enabled to speed up the operation of the logic circuit, and disabled to reduce the peak current of the logic circuit. The additional transistor is enabled by a voltage detection signal, which is active when the operating voltage of the chip is at a low level and inactive when the operating voltage of the chip is at a high level.

Sense amplifier driver having variable power-supply voltage

The present invention is a method and apparatus for reducing the peak current for all the bit mats during a CAS-before-RAs refresh operation of a DRAM. To this end, a circuit is created to detect a CAS-before-RAS refresh operation. When a CBR refresh is detected, the amplifying of the bit mats are offset from each other, thereby staggering the time when each bit mat draws its peak current. In an alternative embodiment, when a CBR refresh is detected, the activation of the word lines are offset from each other, thereby staggering the time when each bit mat draws its peak current.

Semiconductor integrated circuit device having means for peak current

A CMOS sense amplifier circuit for a dynamic read/write memory employs cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through transistors activated by sense clocks. The differential inputs of the sense amplifier are connected to the bit lines through coupling transistors which are held on when the word line and dummy line go high, then are shut off while the sense amplifier is activated by the sense clocks; the coupling transistors are then turned on for selected columns before being turned on for non-selected columns. The current needed to charge and discharge the bit lines is thus spread out, and the peak current is decreased.

CMOS sense amplifier

A system for real-time digital processing of a video signal using a large number of one-bit serial processor elements each of which operates on one pixel of a horizontal scan. The video signal is converted to digital by an A-to-D converter, and stored in a set of input registers, one register for each processor element. All of these input registers are loaded during a horizontal scan, as the input registers are addressed in sequence by a commutator. Each processor element includes a one-bit binary adder, a set of one-bit registers, and two one-bit wide data memories of a size to store data from several scans. The processor elements are all controlled in common by a sequencer, a state machine or a processor. The processed video data is transferred to an output register for each processor element, from which it is converted to a video signal by a D-to-A converter. A frame memory may be used to save a processed frame for use in convolving the next frame; the input of the frame memory is taken at the output registers, and the frame memory output is applied to the input registers.

Serial video processor

A test validation process for a semiconductor device applies signals indicating a test mode to the semiconductor device. The device produces output signals and the output signals are read to determine whether the device is in the indicated test mode. The test mode is conducted by operating the device. The output signals are read upon completion of the test mode to determine if the device is still in the indicated test mode. The test validation method is useful for memory chips and particularly Dynamic Random Access Memory, DRAM, devices that are burn-in stress tested.

Test validation method for a semiconductor memory device

CMOS sense amplifier with bit line isolation

A CMOS sense amplifier circuit for a dynamic read/write memory employs cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through two separate sets of P and N channel transistors selectively activated by sense clocks. The return transistors are activated for either fast or slow sensing, depending upon the address input. The selected columns are sensed at maximum speed, and non-selected columns which are only being refreshed are sensed at a slower speed. A large return transistor is switched into the circuit only for fast sensing, and other smaller transistors perform the slow sense function with high resistance returns to the supply so peak current is lower. The current needed to charge and discharge the bit lines is thus spread out, and the peak current is decreased.

Sense amplifier with reduced instantaneous power

A CMOS sense amplifier for a dynamic read/write memory employs a latch circuit with cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through P and N channel transistors selectively activated by sense clocks. Differential inputs of the sense amplifier are connected to the bit lines. The N-channel transistors are employed for initial sensing, and then both N-channel and P-channel transistors in sequential order for amplification and restoring the 1-level. This results in better balance, and smaller N and P channel latch transistors may be used, saving area, saving power and increasing speed.

CMOS sense amplifier with N-channel sensing

A semiconductor dynamic read/write memory circuit using one-transistor storage cells and balanced bit lines with differential sense amplifiers employs dummy capacitors which are the same size as the storage capacitors. The dummy cell produces a signal on the bit line half that of the storage cell due to a level-shift circuitry connected to the dummy cells. The dummy capacitor is precharged to a reference voltage, and at the beginning of an active cycle the dummy capacitor is charge-shared with another capacitance of the same size, to change the reference level. The net signal is thus equal to that of a capacitor one-half the size of the storage capacitors.

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Houston, TX, United States of America

Adin E Hyslop