University of Florida Research Foundation Inc

Adib Nahiyan

Mark M Tehranipoor

Domenic J Forte

Farimah Farahmandi

Fahim Rahman

Andrew C Stern

Mohammad Sazadur Rahman

Jungmin Park

Methods, apparatus and computer program product for protecting a confidential integrated circuit design process. The computer-implemented method includes receiving a design specification dataset from a first untrusted computing device; extracting confidential design specification data from the design specification dataset; encrypting the confidential design specification data to produce encrypted confidential design specification data; generate a first encryption key to be associated with the encrypted confidential design specification data; retrieving a confidential design specification data subset for replacing a design element subset with a security hard macro (SHM) placeholder design element set; generating a security hard macro (SHM) placeholder feature set comprising those security hard macro (SHM) placeholder features representing mappings from the confidential design specification data subset to the SHM placeholder design element set; and transmitting, to the first untrusted computing device, the encrypted confidential design specification data, the first encryption key, and the SHM placeholder feature set.

Method, apparatus and computer program product for protecting confidential integrated circuit design

Various examples are provided related to power side-channel vulnerability assessment. In one example, a method includes identifying target registers in an IC design; generating input patterns associated with a target function that can generate a power difference in the target registers when processing the target function; determining a side-channel vulnerability (SCV) metric using the power difference produced by the input patterns; and identifying a vulnerability in the IC design using the SCV metric. Identification of the vulnerability allows for modification of the IC design at an early stage, which can avoid power side-channel attacks (e.g., DPA and CPA) in the fabricated IC design. The method can be used for pre-silicon power side-channel leakage assessment of IC designs such as, e.g., cryptographic and non-cryptographic circuits.

CAD framework for power side-channel vulnerability assessment

Disclosed are various embodiments for detecting hardware Trojans through information flow security verification. A file comprising register transfer level (HDL) code for an intellectual property core is loaded from memory. An asset within the intellectual property core is identified. An integrity verification or confidentiality verification of the HDL code that represents the asset is performed. An integrity violation or confidentiality violation within the HDL code as a result of performance of the integrity verification or confidentiality violation on the HDL code that represents the asset is detected. A malicious control point or a malicious observation point linked to the asset is identified. Finally, a trigger circuit for a hardware Trojan is identified in response to identification of the malicious control point or malicious observation point.

Hardware trojan detection through information flow security verification

A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a &#x3c6;-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the &#x3c6;-bit protected Obfuscation Key generated by the LFSR, and output k&#x2514;&#x3c6;&#xd7;&#x3b1;&#x2518;-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.

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Gainesville, FL, United States of America

Adib Nahiyan