Ams Sensors Belgium Bvba

Ams Sensors USA Inc.

Other

Imec

Ams Ag

Katholieke Universiteit Leuven

Ams Sensors Belgium Bv

Imec Vzw

Adi Xhakoni

Denver Lloyd

Scott Johnson

Guy Meynants

Tim Blanchaert

Jan Bogaerts

Kevin Fronczak

Muhammad Maksudur Rahman

Georges Gielen

David San Segundo Bello

Koen Ruythooren

David Sackett

Ali Jaderi

Xiaoliang Ge

Corneliu-Mihai Tobescu

An image sensor arrangement includes a first sensor layer having a first group of pixels. Each pixel of the first group includes a photodiode configured to detect electromagnetic radiation in a first wavelength range. The image sensor arrangement also includes a second sensor layer having a second group of pixels. Each pixel of the second group includes a photodiode configured to detect electromagnetic radiation in a second wavelength range. The image sensory arrangement further includes a readout layer having a readout circuit configured to read out electrical signals from the pixels of the first and the second group. The second sensor layer is arranged between the first sensor layer and the readout layer. The second wavelength range is outside a wavelength range detectable by the first sensor layer. The first sensor layer is attached to the second sensor layer by hybrid bonding.

Image sensor arrangement, image sensor device and method for operating an image sensor arrangement

In an embodiment a method for operating a pixel arrangement includes, during an exposure period, accumulating, by a photodetector, in a first integration period, charge carriers, pulsing, at an end of the first integration period, a transfer transistor to a first voltage level for transferring a portion of the accumulated charge carriers to a diffusion node, wherein the portion is configured to be drained to a supply voltage, continuing, by the photodetector, to accumulate, in a second integration period, charge carriers, after the second integration period, pulsing the transfer transistor to a respective further voltage level with at least one additional pulse, wherein, with each additional pulse, an additional portion of the accumulated charge carriers is configured to be drained to the supply voltage, and wherein each additional pulse is followed by an additional continued accumulation of charge carriers in a respective additional integration period with the photodetector.

Self calibrating barrier modulation pixel

A pixel includes a transfer gate, and a sample structure having a first sample stage and a second sample stage. The transfer gate and the first and the second sample stages are configured to be operated in conjunction with a light source in response to a control signal. The first sample stage is configured to sample a first sample value that depends on radiation incident on the photosensitive element from an object or a scene that is illuminated by the light source emitting light at a first output power, while the second sample stage is configured to sample a second sample value that depends on radiation incident on the photosensitive element from the object or the scene that is illuminated by the light source emitting light at a second output power. The first output power is different, in particular significantly different, from the second output power.

Pixel, electric device and method having a transfer gate and sample stages configured to be operated in conjunction with a light source in response to a control signal

A pixel cell comprises a plurality of pixels, each pixel comprising a photodiode, a readout circuit comprising a first readout component and a second readout component, wherein a first group of the pixels is configured to detect electromagnetic radiation in a first wavelength range, a second group of the pixels is configured to detect electromagnetic radiation in a second wavelength range, the first readout component is connected with the first group of pixels, the second readout component is connected with the second group of pixels, the first wavelength range is different from the second wavelength range, and the second readout component comprises a plurality of storage capacitors, wherein each pixel of the second group of pixels is assigned to at least one of the storage capacitors, or the second readout component comprises a memory element. Furthermore, a method for operating a pixel cell is provided.

Pixel cell, image sensor and method for operating a pixel cell with two readout components

In an embodiment a pixel arrangement includes a photodetector configured to accumulate charge carriers by converting electromagnetic radiation, a transfer transistor electrically coupled to the photodetector, a diffusion node electrically coupled to the transfer transistor, a reset transistor electrically coupled to the diffusion node and to a pixel supply voltage and a sample-and-hold stage including at least a first capacitor and a second capacitor, an input of the sample-and-hold stage being electrically coupled to the diffusion node via an amplifier, wherein the transfer transistor is configured to be pulsed to different voltage levels for transferring parts of the accumulated charge carriers to the diffusion node, wherein at least the second capacitor is configured to store a low conversion gain signal representing a first part of the accumulated charge carriers, and wherein the first capacitor is configured to store a high conversion gain signal representing a remaining part of the accumulated charge carriers.

In an embodiment a pixel arrangement includes at least one photodiode configured to convert electromagnetic radiation into a respective charge signal, a transfer gate between the photodiode and a capacitance for transferring the respective charge signal to the capacitance, a reset gate electrically coupled to the capacitance, the reset gate configured to reset the capacitance, an amplifier electrically connected to the capacitance and configured to generate, based on the respective charge signal and on a sensitivity mode, a respective amplified signal being a low sensitivity signal or a high sensitivity signal, respectively, wherein the low sensitivity signal and the high sensitivity signal are based on a common noise level, a first capacitor configured to store the high sensitivity signal, a second capacitor configured to store the low sensitivity signal, a first switch between an output terminal of the amplifier and the first capacitor and a second switch between the output terminal of the amplifier and the second capacitor.

Pixel arrangement, image sensor and method of operating a pixel arrangement

A pixel arrangement comprises a photodiode, a circuit node, a transfer transistor coupled to the photodiode and to the circuit node, an amplifier with an input coupled to the circuit node, a first and a second capacitor, a first transistor coupled to an output of the amplifier and to the first capacitor, a second transistor coupled to the first transistor and to the second capacitor, and a coupling transistor coupled to the circuit node and to the second capacitor.

Pixel arrangement and method for operating a pixel arrangement

An image sensor system has a pixel array with a plurality of pixels, each of the pixels comprising a photodiode, a pixel buffer and a transfer gate coupled between the photodiode and an input of the pixel buffer. A voltage supply block is configured to generate a pixel supply voltage from an input voltage based on a first reference voltage and to provide the pixel supply voltage to the pixel array. A calibration processing block is configured to determine an average pixel signal based on an average of individual pixel signals at outputs of the pixels of the pixel array and to determine a correction value based on the average pixel signal and a reference pixel signal. A correction processing block is configured to determine the first reference voltage based on a combination of a second reference voltage and the correction value.

Image sensor system, electronic device and method for operating an image sensor

An image sensor includes a pixel array including a plurality of pixels each including a photosensitive element, and a readout circuit, wherein the pixels are arranged in at least two columns, within each column at least some of the pixels of the column are connected with a common column bus, respectively, for each column the readout circuit includes a first analog-to-digital converter (ADC) and a second ADC, for each column the first ADC is connected with the column bus, and for each column the second ADC is connectable with at least one of the column bus and a reference potential or the second ADC is connected with one optically shielded pixel of the pixel array.

Image sensor and method for operating an image sensor

An image sensor is proposed to have a stack with at least a pixel array tier and a control logic tier. The pixel array tier comprises an array of pixels which are arranged into pixel columns n, each pixel column n comprising a number of N sub-columns: Each sub-column is denoted by N(n,i) with 1&#x2264;i&#x2264;N. The control logic tier comprises an array of analog-to-digital-converters which are arranged into ADC columns m, wherein each analog-to-digital converter comprises a number of M stages. Each stage is denoted by M(m,j) with 1&#x2264;j&#x2264;M, Furthermore, each respective sub-column N(n,i) is electrically connected to a dedicated stage M(m,j=i) and the stages M(m,j) are electrically interconnected to form the analog-to-digital converters, respectively. The control logic tier is arranged to sequentially read out the sub-columns N(n,i), wherein the stages M(m,j=i) dedicated to the sub-columns N(n,i) are arranged as input stages to sequentially receive signal levels of the pixels in the sub-columns N(n,i), respectively. The input stages are arranged to perform on the sequentially received signal levels a coarse first analog-to-digital conversion. The remaining stages M(m,j&#x2260;i) are arranged to sequentially perform finer analog-to-digital conversions of the received signal levels.

Image sensor and method for readout of an image sensor

In one embodiment an analog-to-digital converter circuit has an input for receiving a first analog signal level and a second analog signal level, a ramp generator adapted to provide a ramp signal, a comparison unit coupled to the input and the ramp generator, a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, and an output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level. Therein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and the falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal.

Analog-to-digital converter circuit and method for analog-to-digital conversion

An analog-to-digital converter () comprises an analog signal input () for receiving an analog signal and an amplifying stage () configured to generate a set of N amplified analog signals, where N is an integer &#x2265;2. The set of N signals have different gains. The ADC has a ramp signal input () for receiving a ramp signal and a clock input () for receiving at least one clock signal. A comparison stage () is connected to the set of amplified analog signals (SigG, SigG) and to the ramp signal input (). The comparison stage () is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage () based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

Analog-to-digital conversion and method of analog-to-digital conversion

An analog-to-digital converter () for an imaging device comprises an analog signal input () for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs () for receiving N ramp signals, where N is an integer &#x2265;2. The N ramp signals have different slopes. The ADC has a clock input () for receiving at least one clock signal. A comparison stage () is connected to the ramp signal inputs and to the analog signal input. The comparison stage () is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage () is configured to control a counter stage () based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

A method of increasing dynamic range of pixels in an imaging sensor is disclosed. In one aspect, two image captures are performed, one at a first short integration time and one at a second optimum integration time. An electrical value obtained from a pixel or group of pixels at the first short integration time is used to predict the second integration time using a comparison with a set of reference values. The reference values relate to a saturation electrical value for each pixel or group of pixels to predict the second integration time. The first short integration time is determined as a fractional multiple of the saturation electrical value. The second integration times are such that there is no saturation of the pixel or group of pixels. Adjustments can be made to the reference values to allow for offset immunity and variability in light levels during the second integration time.

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Kessel-lo, Belgium

Adi Xhakoni