Freescale Semiconductor,inc.

Nxp USA, Inc.

Marvell Asia Pte., Ltd.

Adi Katz

Evgeni Ginzburg

Eliya Babitsky

Moran Noiman

Yaakov Yehezkel

Shai Koren

Gil Moran

Tal Robinson

Yuval Harari

Ron Treves

Ofer Halili

Eran Glickman

Stefania Gandal

Moti Dvir

Bernard Francois St-Denis

Eliezer Weitz

Ruven Torok

Avi Hagai

Moti Kurnick

John F Pillar

Yoram Yeivin

Yaron Alankry

Avi Haimzon

Erez Arbel-Meirovich

Noam Efrati

Avi Shalev

Klod Asoline

Erez Shaizaf

Roman Nos

Ilan Strulovici

Yaron Bareket

Ofer Lavi

Keren Guy

Mark Glazman

Yossi Socoletzki

An address translation system, method and device including a translation extension unit associated with a client and having a client address translation cache storing a client cache of the address translations. When virtual address of a translation request from the client is the same as the virtual address of an address translation of the client cache, the translation extension unit returns the physical address that is mapped to the virtual address according to the address translation to the client without transmitting the translation request to a memory management unit that maintains a page table of all the translations and a translation lookaside buffer with a subset of the translations.

Address translation system, method and device

A circuit and corresponding method perform timestamp filtering. The circuit includes recursive filter logic that implements a recursive least-squares (RLS) filter. The circuit (i) generates a filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic applies the RLS filter to a portion of the received timestamp. A number of bits of the portion is less relative to a total number of bits of the received timestamp. The circuit outputs the filtered timestamp generated. Applying the RLS filter to the portion enables the circuit to be more efficient (e.g., smaller adders, fewer flipflops, etc.), thereby reducing area and power consumption of the circuit.

Circuit and method for timestamp filtering with RLS filter

A circuit and corresponding method generate a filtered timestamp. The circuit comprises recursive filter logic. The circuit generates the filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic reduces jitter in the filtered timestamp relative to jitter of the received timestamp. The jitter represents a deviation of the received timestamp from a target (ideal) timestamp. The circuit outputs the filtered timestamp generated. The filtered timestamp is a more accurate representation of the target timestamp, relative to the received timestamp, due to the jitter reduced.

Circuit and method for timestamp jitter reduction

A method of reducing jitter in transmission of a timestamp across a clock domain boundary includes storing N timestamps, generated in N successive clock cycles of an origin clock domain, in N parallel buffers in the origin clock domain under control of a modulo-N counter, transmitting outputs of the N parallel buffers across the clock domain boundary into a destination clock domain along with the modulo-N counter, processing the modulo-N counter in the destination clock domain to derive a selection signal that selects a stable timestamp from among the outputs of the N parallel buffers, and outputting the selected stable timestamp. The modulo-N counter may be Gray-coded modulo-N counter to reduce jitter in the modulo-N counter across the clock domain boundary.

Method and apparatus for passing clock signals between time domains

A circuit and corresponding method perform timestamp filtering. The circuit comprises input format-conversion logic that converts a received timestamp from an original timestamp format to an intermediate timestamp format. The circuit further comprises recursive filter logic coupled to the input format-conversion logic. The recursive filter logic generates a filtered timestamp in the intermediate timestamp format by filtering the received timestamp in the intermediate timestamp format. The circuit further comprises output format-conversion logic coupled to the recursive filter logic. The output format-conversion logic converts the filtered timestamp from the intermediate timestamp format to the original timestamp format and outputs the filtered timestamp in the original timestamp format. Converting the received timestamp into a different format avoids use of complex logic to handle rollover of input values, thereby reducing area and power consumption of the circuit.

Circuit and method for timestamp filtering with input/output format conversion

A method for allocating to a resource, in a system of addressable resources, a hybrid deterministic/random key for access to a second resource, includes maintaining a table of storage positions for key values, searching the table for an available storage position, determining an index, in the table, of the available storage position, generating a random key value associated with location of the second resource, storing the random key value in the storage position, and assembling the index and the random key value into the hybrid key. The index may be most significant bits of the hybrid key, with the random key value being the least significant bits. Alternatively, the index may be least significant bits of the hybrid key, with the random key value being the most significant bits, or the bits of the index may be distributed among bits of the random key value.

Key management for remote device access

A first master receives a first virtual address in a virtual memory, the first virtual address in the virtual memory corresponding, according to a mapping function, to a first physical address of a first physical memory bank which is to be accessed by the first master. The first master accesses the first physical address to perform a first memory operation in the first memory bank. A second master receives a second virtual address in a virtual memory, the second virtual address in the virtual memory corresponding, according to the mapping function, to a second physical address of a second physical memory bank which is to be accessed by the second master. Concurrently with access by the first master to the first physical address, the second master accesses the second physical address to perform a second memory operation in the second physical memory bank.

Accelerating access to memory banks in a data storage system

A packet processing architecture includes a plurality of packet processing stages, wherein at least one of the packet processing stages includes multiple next processing stage modules that are operably coupled to respective further processing stages, wherein the multiple next processing stage modules are dynamically configurable.

Packet processing architecture and method therefor

A network processor has a 'bi-level' architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.

Hash-based packet classification with multiple algorithms at a network processor

A method and apparatus are provided for classifying received network frames () by extracting frame header data (e.g., n-tuple) which is combined with a key insert value (e.g., embedded prefix value 'OP0, OP0, . . . OP0') to generate a lookup key (), where the key insert value is generated by decoding a key composition rule () to extract a constant value (OP0) and a repeat value (OP1), and then replicating the constant value one or more times specified by the repeat value.

Method and apparatus for coding a user defined constant into a key composition rule using variable length command

Methods and systems are disclosed to access memory locations using auxiliary keys in addition to primary keys. Commands are received by a memory management unit to insert or access records in an exact match keyed lookup table where records include keys (i.e., primary keys), auxiliary keys, and data. When a command to insert a new record is received along with key and data, the memory management unit generates a new unique auxiliary key. The auxiliary key includes a table index generated from the key and a collision index that is unique for any records having the same table index. The key, the auxiliary key, and the data for the new record are then stored within the lookup table along with a collision pointer that links records having the same table index. Subsequently, commands to access the new record can selectively use either the original key or the auxiliary key.

Systems and methods to access memory locations in exact match keyed lookup tables using auxiliary keys

A temporal-miss handler includes updating a data leaf in a tree-structured database of a communications processor with a plurality of threads. A search for the data leaf includes generating at least one search result for one of the plurality of threads. A sufficiency of a temporal separation, between updating the data leaf and searching for the data leaf, to retrieve the data leaf is determined. Each search result is cleared when the temporal separation is insufficient. A new search is performed when the temporal separation is insufficient.

Tree-search temporal-miss handling

A data processing device includes a hash table management module that sequentially steps through linear address space of the hash table to identify hash chain in sequential address order. Each identified hash chain is evaluated, before identifying a next hash chain, to remove any entries marked for deletion.

System and method for removing hash table entries

Methods and systems are disclosed for non-intrusive debug processing of network frames. For certain embodiments, a frame parser processes frames from a network interface and generates frame metadata. A key generation engine processes each frame and its related metadata to generate a normal key and a debug key. The same key composition rule formats and key generation engine are used to generate the normal key and the debug key to provide non-intrusive debug processing. Frame classification logic compares the normal key to classification tables to determine a frame classification for the received frame. Separate debug comparison logic compares the debug key to debug reference data/masks to generate debug markers for the received frame. The frame classification and the debug markers for each frame are provided to frame marking logic, and a frame processing engine then processes the resulting marked/classified frames.

Methods and systems for non-intrusive debug processing of network frames

Methods and systems are disclosed to embed valid-field (VF) bits into classification keys for network packet frames. The embedded VF bits allow for extracted data from existing fields associated with frame data to be distinguished from default data used for missing fields where this extracted data and default data has been included within a frame classification key generated for a network packet frame. In certain embodiments, a valid-field field extraction command (VF-FEC) causes a key generator to embed VF bits into a frame classification key, and the logic state of the VF bits are used to distinguish extracted data from default data. Further, the disclosed embodiments allow VF bits to be selectively cleared based upon a bit mask applied prior to embedding of the VF bits. Still further, users can define VF-FECs and other field extraction commands (FECs) for key generation through one or more programmable key composition rules.

Growing community of inventors

Ramat Gan, Israel

Adi Katz