Amazon Technologies, Inc.

Marvell Israel (Misl) Ltd.

Other

Marvell International Limited

Annapuma Labs Ltd.

Annapurna Labs Ltd.

Adi Habusha

Nafea Bshara

Guy Nakibly

Yaniv Shapira

Itai Avron

Georgy Machulsky

Ali Ghassan Saidi

Ofer Naaman

Said Bshara

Gil Stoler

Eric Jason Brandwine

Leah Shalev

Mark Bradley Davis

Matthew Shawn Wilson

Hani Ayoub

Tzachi Zidenberg

Thomas A Volpe

Erez Izenberg

Itay Poleg

Ron Diamant

Anthony Nicholas Liguori

Ronen Shitrit

Ohad Gdalyahu

Barak Wasserstrom

Eitan Joshua

Uwe Dannowski

Uri Leder

Tarek Rohana

Netanel Israel Belgazal

Rabeeh Khoury

Roi Ben Haim

Simaan Bahouth

Nir Bar-Or

Osnat Katz

Michael Zuzovski

Darin Lee Frink

Sujat Jamil

Roland Alexander Paterson-Jones

David E Miner

Martin Thomas Pohlack

Erez Sabbag

Noam Mizrahi

Stephen Edward Schmidt

Dana Michelle Vantrease

Tom Marko Hameenanttila

Christopher James BeSerra

Joseph Anthony Delgross

Tom Kolan

Saar Gross

Dan Ilan

Ziv Harel

Alon Pais

Shaul Chapman

Benny Pollak

Frank O'Bleness

Jeffrey Kehl

Peter Barry

Sergey Kleyman

Svetlana Kantorovych

Daniel Joseph Grey

Tal Zilcer

Yaakov Gendel

Nicolas Worms

Leonid Froenchenko

Aviv Bakal

Ilan Wachtel

Maxim Tzipori

Gal Paikin

Lev Makovsky

Lior Podorowski

Zeev Zilberman

Hardware errors can be detected by generating a plurality of test templates to perform testing on an integrated circuit (IC) device. A set of random tests can be generated corresponding to the plurality of test templates. The set of random tests can be executed on the IC device for multiple passes, and the results of the multiple passes can be compared to detect the hardware error in the IC device. The set of random tests can be generated as a binary image for execution on the IC device. The IC device may include multiple processing cores, and executing the multiple passes may include changing logical role of each processing core between subsequent passes. The set of random tests can be executed in a bare-metal mode, or at an application level of the IC device.

Detecting hardware errors

An input/output (I/O) device can initiate data migration of a virtual machine (VM) instance from a source device to a target device. The data migration of the VM instance may include migrating the data for the VM instance and tag data associated with the data. The data for the VM instance and the tag data may be stored together in a source memory. A first read request from the I/O device can enable a memory controller in the source device to read the data for the VM instance and the tag data together, store the tag data in a tag data buffer, and transmit the data for the VM instance to the target device. A second read request from the I/O device can read the stored tag data from the tag data buffer and transmit to the target device. The target device can write the data for the VM instance together with the tag data in the target memory.

Data migration with metadata

The coherency of data can be maintained even for accelerators that may not directly support, or be part of, a coherency protocol or domain. A pair of agents can be utilized that include an application accelerator agent and a coherent agent. The coherent agent can support the coherency protocol and track coherency information for data in the coherency environment, to ensure coherent access to the data. The application accelerator agent can work with the coherent agent to obtain the data according to the coherency protocol, then perform operations on the data corresponding to a respective application or process. Such an approach enables an accelerator to function like a processor or processor core that otherwise supports the coherency protocol and is part of the coherency domain. A single coherent agent can be used to maintain coherency information for multiple other components or agents.

Coherent agents for memory access

A host device may include an interconnect, a host memory, and a set of processor cores. A processor core may execute a VM assigned to a cryptographic key and may send a request to access a physical address in the host memory toward the interconnect. An enforcer device may receive the request and extract a key identifier from the request. The enforcer device may determine whether to allow the request to access the physical address via the interconnect based on the key identifier and a list of allowed keys stored on the enforcer device. If the enforcer device determines to not allow the request to access, the enforcer device may modify the physical address and/or the key identifier of the request.

Limiting use of encryption keys in an integrated circuit device

Methods and integrated circuit devices for recording memory-side page activity are provided. Memory systems typically have a combination of faster memory devices and slower memory devices. Frequently accessed memory pages (hot pages) should be maintained in the faster memory devices while less frequently accessed memory pages (cold pages) should be maintained in the slower memory devices. To determine the memory pages that should be moved between the faster memory devices and the slower memory devices, counters may be implemented to count transactions to the memory pages. The counter values may be periodically checked to identify memory pages that can be moved from faster memory devices to slower memory devices, and vice-versa.

Memory-side page activity recorder

Techniques for emulating a configuration space may include emulating a set of configuration registers for a set of functions corresponding to a type of peripheral device. The set of functions can include a physical function and a virtual function associated with the physical function. A configuration access request can be processed by retrieving an emulated configuration register from the emulated configuration space, and logging incoming configuration access requests in a configuration transaction log to track configuration accesses.

Emulated endpoint configuration

A coherent connection and a non-coherent connection are provided between system-on-chips (SoCs). The coherent connection can be coupled to coherent interconnects on the SoCs, and the non-coherent connection can be coupled to non-coherent interconnects on the SoCs. An input/output (I/O) transaction from an I/O device on a first SoC that is targeted to a second SoC can be transmitted via the non-coherent connection, and a processor transaction from the first SoC that is targeted to the second SoC can be transmitted via the coherent connection.

Non-coherent and coherent connections in a multi-chip system

A system includes an obsolete cache-line vector having a plurality of memory elements, wherein each memory element has a one-to-one correspondence to a cache line entry of a cache memory. The vector can capture cache line errors that occur at different times from an error detection logic associated with the cache memory. A counter can be coupled to the obsolete cache-line vector for tracking how many of the memory elements in the vector are activated. When a predetermined threshold is reached, a threshold comparator can release a trigger for further analysis. An error events logger can be used to track all of the errors that occurred. The error events logger can also use a time stamp, which can assist the RAS system in analyzing a correlation between the errors, such as patterns that occur and time differences between the errors.

Cache memory error analysis and management thereof

Systems and methods are provided to differentiate different types of traffic going through the same physical channel such that the traffic flow for different traffic types does not impact each other. The physical channel can be configured to support a plurality of virtual channels. Each transaction that needs to be communicated through the physical channel can be classified into a certain traffic type, and each traffic type can be assigned to a virtual channel. Each transaction can be communicated on a respective virtual channel based on the corresponding traffic type. If the traffic flow through a first virtual channel for a transaction slows down, the traffic flow through a second virtual channel for another transaction can continue without getting impacted by the slow down on the first virtual channel.

Traffic separation in a multi-chip system

An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

Direct injection of a virtual interrupt

A computer system and methods are disclosed for mitigating side-channel attacks using memory aliasing. The computer system includes a memory, a memory controller and a cache. Responsive to determining to share a memory location among processes, the address of the memory may be aliased to another address within the same address space, with the address and aliased address assigned to respective ones of the processes. The memory controller manages the address space according to an aliasing region and a non-aliasing region, with addresses corresponding to the non-aliasing region being passed through to the memory. Addresses corresponding to the aliasing region are translated by the memory controller to match corresponding non-aliased memory addresses allowing aliased and non-aliased addresses to access same memory locations. A cache may cache accesses to memory addresses, including the non-aliased and aliased addresses, with different cache locations for selected according to the respective addresses of memory.

Memory de-duplication using physical memory aliases

Ordering rules, such as those enforced by the peripheral component interconnect express (PCIe) protocol for data communications, can be intelligently enforced for independent transactions. A single device might host or be associated with multiple PCIe devices, such as virtual machines, and treating requests from these separate PCIe devices as coming from separate domains enables the ordering rules to be bypassed for certain transactions. Further, since a virtual machine might host multiple applications or be associated with multiple processors that can submit independent requests, the ordering rules can be bypassed at the transaction level in at least some instances. The ability to intelligently bypass ordering rules can help to improve the performance of the overall system, as requests do not need to be unnecessarily delayed and data storage capacity can be more fully utilized.

Transaction ordering management

A system captures errors and stores an obsolete line bit qualifier per cache entry that can be used to dynamically mark a specific cache entry as obsolete. For example, the cache entry can be marked as obsolete after detecting repetitive single-bit errors on a same cache entry within a predetermined period of time. For cache lines marked as obsolete, a cache controller can ensure that the cache line entry remains unused. The detection of a repetitive single-bit error can be accomplished by implementing a counter per cache entry and a timer. The counter counts errors within a timer window, and a repetitive error is reported if the counter reaches a threshold level. By catching repetitive single-bit errors before such errors spread to multi-bit errors, the system can increase the life span of the server computer.

Increasing of cache reliability lifetime through dynamic invalidation and deactivation of problematic cache lines

Techniques are disclosed for transferring a message between a sender agent and a receiver agent via a shared memory having a main memory and a cache. Feedback data indicative of a number of read messages in the shared memory is generated by the receiver agent. The feedback data is sent from the receiver agent to the sender agent. A number of unread messages in the shared memory is estimated by the sender agent based on the number of read messages. A threshold for implementing a caching policy is set by the sender agent based on the feedback data. The message is designated as cacheable if the number of unread messages is less than the threshold and as non-cacheable if the number of unread messages is greater than the threshold. The message is written to the shared memory based on the designation.

Configurable caching policy for transferring data via shared memory

Execution flows of a program can be characterized by a series of execution events. The rates at which these execution events occur for a particular program can be collected periodically, and the execution events statistics can be utilized for both training a machine learning model, and later on for making classification inferences to determine whether a program run contains any abnormality. When an abnormality is encountered, an alert can be generated and provided to supervisory logic of a computing system to indicate that an abnormal program flow has been detected.

Program flow classification

Growing community of inventors

Moshav Alonei Abba, Israel

Adi Habusha