Motorola Corporation

Other

Adelore F Petrie

Rupin J Javeri

Thomas F Karlmann

Randall C Gray

Richard A Comroe

Arthur J Edwards

Roy E Hunninghaus

Steven G Parmelee

John Y Babico

A method and apparatus is disclosed for forming a binary level output signal which has a single transition representative of a threshold crossing in a sensor output signal. The sensor output signal is applied to the inputs of two signal processing circuits, the first of which develops a first signal having a relatively fast transition representing the threshold crossing. The second circuit develops a second output signal that is representative of an integrated version of the sensor signal. In the preferred embodiment, a flip-flop receives the first signal at a clock input and the second signal at a data input. The flip-flop's set input may also receive the second signal. The resultant output signal from the flip-flop has but a single transition representing the threshold crossing, irrespective of noise-induced threshold crossings in the sensor output signal.

Threshold crossing detector

A short-circuit protected switched output circuit having: an input node (I10) for receiving an input switching signal; an output node (O10) for outputting a switched output signal; switch means (Q10) connected between the input and output nodes; and a Schmitt trigger NAND gate oscillator arrangement (C10, D11, D12, NG10, R12, R13, R14) having an input coupled to the output node and having an output coupled via diode means to the input node, whereby the oscillator arrangement produces a low frequency, low duty-cycle, fixed-frequency signal at the output node in the event of the output node being short-circuited. An alternative circuit using a Schmitt trigger inverter are also disclosed.

Short-circuit protected switched output circuit

An improved dual limit solenoid driver control circuit is disclosed in which solenoid current is sensed and provided as an input to two separate comparators (24, 25). Each comparator receives, during a solenoid pull-in (initial) period (T.sub.1), fixed maximum and minimum reference threshold levels which determine the maximum and minimum current limits (I.sub.max, I.sub.min) for solenoid current during initial pull-in excitation. Subsequently during a hold period T.sub.2 following the pull-in period, each of the comparators receives different maximum and minimum thresholds so as to establish holding solenoid current limits (H.sub.max, H.sub.min). The outputs of the compartors are connected as inputs to a set/reset flip flop (32) whose output controls the operation of a solenoid driver circuit (15). A monostable multivibrator (33) reacts to an initial control pulse (41) to produce a predetermined pull-in time pulse (43) that results in the maximum and minimum pull-in solenoid current limits. The comparator thresholds are provided by a fixed resistor divider circuit (27, 29, 31) which receives a pull-in signal from the monostable multivibrator. The pull-in period (T.sub.1) is independent of the sensed solenoid current, and the switching thresholds are fixed and independent of the magnitude of the solenoid current during the pull-in and hold periods. The above configuration provides improved performance and stability, and is readily implemented with just a few components.

Dual limit solenoid driver control circuit

In a solenoid fuel injection system, an output transistor (16) receives switching signals to control through current therein which is provided to a solenoid fuel injection coil (11) in series with a current sensing resistor (17). A current control circuit (12) provides pulse width modulation control of solenoid current by monitoring the voltage across the sensing resistor. The fault detection circuit provides separate fault signals for short circuits at either the first or second end terminals (E, H) of the solenoid coil. Separate voltage comparators (18, 23) monitor voltages at the first and second end terminals, and separate delay timers (20, 25) effectively gate the comparator outputs to indicate actual detected short circuits. Each of the fault detection signals sets a fault latch (22) which then acts to reduce current through the output transistor and coil. The fault latch is periodically reset. For a fault detection, the output transistor is protected from excessive current resulting from a short circuit at one end terminal (H). The transistor and coil are also protected from a short circuit at the other end terminal (E) which results in the lack of a current sense signal causing the controller (12) to attempt to maintain the output transistor constantly on.

Fault detection circuit

A solenoid driver control circuit for use with solenoids, the circuit including a current sense unit (12) for providing a current sense signal and a solenoid drive unit (13) for selectively allowing current to flow through the solenoid (11) from a power source (14). The circuit also includes a threshold comparator unit (17) for comparing threshold signals with the current sense signal and for providing an output signal that can control the solenoid drive unit (13), a minimum threshold unit (18) for providing a minimum threshold, a maximum threshold unit (19) for initially providing a maximum threshold until a peak current flow through the solenoid (11) has been established, a first timing unit (21) to periodically provide increased threshold signals for specified durations of time, and a second timing unit (41) for initially providing an increased minimum threshold signal at the outset of a control cycle. The device provides a minimum current flow through the solenoid (11) at all times during a control cycle and utilizes time control to realize the desired solenoid current waveform.

Solenoid driver control unit

A fault tolerance signal receiver (10) for use with differential voltage level transmission systems from which two voltage levels may be substantially simultaneously sensed to allow the two voltage levels to be decoded into digital signals. The receiver (10) includes an input unit (11) for receiving the two voltage levels and for producing outputs related to these two voltage levels, a first logic unit (12) for receiving the output from the input unit and for producing an output, with the output being selectively variable when the two voltage levels are valid and non-variable when the two voltage levels are invalid due to the presence of a fault condition in the transmission system, and a second logic unit (13) for receiving the output of the first logic unit (12) and the input unit (11) for correctly outputting a decoded digital signal (17) provided that the transmission system has no more than one fault condition present thereon. A fault condition signal (27) may also be provided.

Fault tolerant receiver

Digital circuitry adaptable for controlling dwell in a spark and dwell ignition control system is disclosed. Maximum advance and reference sensors are utilized to produce pulse transitions which determine positions of maximum and minimum possible advance for spark ignition with respect to the position of the engine crankshaft. For each maximum advance sensor pulse transition a main counter starts a sequential running count of speed independent clock pulses wherein the maximum count obtained by the counter is related to engine crankshaft speed. The running and maximum counts of the main counter are utilized by dwell circuitry to determine the time prior to the next maximum advance pulse at which spark coil excitation should occur.

Digital circuitry for producing indicative signals at predetermined

A speed-dependent ignition controller and method utilizes a sensor output signal to provide spark occurrence and dwell initiation at retard and advance angles for an internal combustion engine. The sensor signal has a pulse width proportional to the difference between a desired ignition advance and retard angle. At low rpm, the sensor signal is inverted to produce a retarded ignition angle while at high rpm's the signal is utilized without inversion to produce an advance ignition angle.

Speed dependent ignition controller and method

Information is derived from two given sets of sensor output pulses relating to crankshaft position for use in determining the proper cylinder to be fired, the spark time and the dwell. The spark is enabled only after the crankshaft position is known, and noise, including the spark itself, is prevented from interfering with the system operation.

Electronic ignition input logic

A four-cylinder engine control system (10) for controlling the functions of ignition or fuel injection is disclosed. The control system includes cylinder identification apparatus (30, 50, 60) which operates in conjunction with a rotary member (11) rotated by the engine crankshaft having timing projections (14, 17) corresponding to specific rotational positions of the crankshaft. A pair of fixed sensors (20, 21) sense the passage of the timing projections and provide corresponding signals to an engine timing calculation and control circuit (40) which provides control signals that are sequentially selectively routed to control ignition and/or fuel injection of the engine cylinders in a predetermined sequence. One timing projection (14) comprises two individual radial extensions (15, 16) whereas another comprises a single extension (17). Cylinder identification apparatus utilizes sensor pulses (200, 201) provided by the fixed sensors to distinguish between the passage of the pair of extensions versus the passage of the single extension and provide a cylinder identification pulse (207) indicative of the rotational position of the engine crankshaft. This is accomplished by a first pulse reject circuit (60) which provides an output when one of the sensors produces two pulses prior to the other sensor producing a subsequent pulse. This output is then utilized to initialize the sequential gating of control signals to cylinder control apparatus.

Engine control system with cylinder identification apparatus

Digital dwell circuitry for a spark and dwell ignition control system is disclosed. Maximum advance and reference sensors are utilized to produce pulse transitions which determine positions of maximum and minimum possible advance for spark ignition with respect to the position of the engine crankshaft. For each maximum advance sensor pulse transition a main counter starts a sequential running count of speed independent clock pulses wherein the maximum count obtained by the counter is related to engine crankshaft speed. The running and maximum counts of the main counter are utilized by dwell circuitry to determine the time prior to the next maximum advance pulse at which spark coil excitation should occur. The main counter running count also determines several inputs to a read only memory (ROM) circuit whose output controls a rate multiplier. The rate multiplier receives input clock signals, provides selective frequency division for these clock signals in accordance with the ROM output, and the output of the rate multiplier is coupled to an accumulator means whose accumulated count is utilized to determine the occurrence of spark ignition by terminating spark coil excitation.

Digital dwell circuit

The disclosed circuit permits AC coupling of digital waveforms and rejects low frequency interference, yet restores proper waveform even to low frequency digital signals which have suffered waveform distortion by having passed through a transmission channel or storage device with limited low frequency response. Said circuit consists of a differentiator bridged across a non-inverting digital amplifier.

Digital waveform conditioning circuit

Electronic signal processing circuitry for use in the ignition system of an internal combustion engine is disclosed herein. A signal generator which receives crankshaft position pulses from a sensor and produces periodic output pulses which have durations equal to a constant percentage of the period of the input sensor pulses is disclosed. The generator includes a crankshaft position sensor feeding a bistable flip-flop which controls a dual slope integrator circuit having its output coupled to a comparator with the comparator output coupled back to the reset terminal of the flip-flop. The generator produces pulses at the output of the flip-flop which have durations equal to a constant percentage of the period of the crankshaft position sensor pulses. The dual slope integrator circuit produces a periodic ramp (sawtoothed) signal which is processed by a clamping circuit and a comparator to produce an ignition dwell pulse which occurs a fixed time before the occurrence of the crankshaft position sensor pulses. An engine speed monitoring circuit also receives the periodic varying ramp signal produced by the dual slope integrator and via sampling circuitry produces an output signal related to engine speed whose magnitude is updated during each cycle of the crankshaft position pulses.

Ignition dwell circuit for an internal combustion engine

A digital waveform conditioning circuit includes a noninverting amplifier stage. A source of digital information is coupled to the input of the amplifier via a series resistor. The amplifier output is coupled to a digital utilization circuit. A feedback capacitor is coupled between the amplifier input and output terminals to provide integration of unwanted input noise pulses, positive feedback during threshold transitions for fast rise and fall times, and a hold-off voltage for a specified time thereafter to prevent oscillations during said transitions.

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Arlington Heights, IL, United States of America

Adelore F Petrie