Intel Corporation

Tahoe Research, Ltd.

Santa Clara

Adel A Elsherbini

Johanna M Swan

Shawna M Liff

Feras Eid

Aleksandar Aleksov

Telesphor Kamgaing

Georgios C Dogiamis

Sasha N Oster

Henning Braunisch

Krishna Bharath

Gerald S Pasdast

Arun Chandrasekhar

Veronica Aleman Strong

Brandon M Rawlings

Valluri Ramana Rao

James S Clarke

Mathew J Manusharow

Thomas L Sounart

Richard J Dischler

Patrick R Morrow

Kimin Jun

Vijay K Nair

Javier Soto Gonzalez

Javier A Falcon

William J Lambert

Jeanette M Roberts

Roman Caudillo

Yidnekachew S Mekonnen

Brennen Karl Mueller

Beomseok Choi

Van H Le

Kaladhar Radhakrishnan

Amit S Baxi

Braxton L Lathrop

Vincent S Mageshkumar

Nadine L Dabby

Ravi Pillarisetty

Robert L Sankman

Paul B Fischer

John Stephen Guzek

Nicole K Thomas

Zhichao Zhang

Hubert C George

David J Michalak

Zachary R Yoscovits

Joshua Heppner

Han Wui Then

Kristof Darmawikarta

Robert Alan May

Ravindranath Vithal Mahajan

Nitin A Deshpande

Zhiguo Qian

Sri Ranga Sai Boyapati

Lester Lampert

Suddhasattwa Nad

Jimin Yao

Meizi Jiao

Mauro J Kobrinsky

Fay Hua

Kanwaljit Singh

Baris Bicen

Kemal Aygun

Lakshman Krishnamurthy

Mihir K Roy

Yoshihiro Tomita

Vivek Raghunathan

Kenneth D Shoemaker

Gaurav Chawla

Kumar Ranganathan

Kevin P O'brien

Robert S Chau

Gilbert W Dewey

Marko Radosavljevic

Debendra Das Sharma

Bernhard Raaf

Debendra Mallik

Srinivas V Pietambaram

Min Huang

Kevin O'Brien

Omkar G Karhade

Randy B Osborne

Chuan Hu

Pooya Tadayon

Zuoguo Wu

Stefano Pellerano

Wilfred Gomes

James Chris Matayabas, Jr

Yonggang Li

Dilan Seneviratne

Ravi V Mahajan

Sriram Srinivasan

David Johnston

Srikant Nekkanty

Emanuel Cohen

Rachael Jade Parker

Julien Sebot

Hyung-Jin Lee

Christopher Schaef

Charles A Gealer

Pablo Herrero

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

Power delivery through capacitor-dies in a multi-layered microelectronic assembly

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.

Direct bonding in microelectronic assemblies

Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

Composite interposer structure and method of providing same

In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.

Semiconductor packages with antennas

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

Microelectronic assemblies having a hybrid bonded interposer for die-to-die fan-out scaling

Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

Thermal performance in hybrid bonded 3D die stacks

An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

Skip level vias in metallization layers for integrated circuit devices

A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

Packaging architecture for disaggregated integrated voltage regulators

An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

Liquid cooled interposer for integrated circuit stack

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Microelectronic assemblies with communication networks

In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

Conformal power delivery structure for direct chip attach architectures

Growing community of inventors

Tempe, AZ, United States of America

Adel A Elsherbini