Intel Corporation

Cisco Technology, Inc.

Adee Ofir Ran

Kent C Lusted

Amir Mezer

Assaf Benhamou

Ehud Udi Shoor

Itamar Fredi Levin

Kevan A Lillie

Richard I Mellitz

Yoni Landau

Dror Lazar

Amir Laufer

Alon Meisler

Itay Tamir

Yaakov Dalsace

Shlomi Lalush

Alexander Pogrebinsky

Aviran Kadosh

David G Ellis

Mark Andrew Gustlin

Ariel Cohen

Yoel Krupnik

David L Chalupsky

Yaniv Hadar

Ram Livne

Tomer Geva

Eran Nussbaum

Stephen J Peters

Itamar Levin

Lior Horwitz

Joel Dror

Harry Birenboim

Gil Afriat

Ro'ee Eitan

Vladislav Tsirkin

Tomer Fael

Sanjay R Ravi

Nishantkumar Shah

Mor Cohen

Jeffrey M Shuey

Assaf Issachar

Golan Perry

Roi Bar

Rushdy A Saba

David Golodni

Liran Brecher

Ophir Gazinski

Symbol multiplexing Physical Medium Attachment (PMA) may be provided. A plurality of first lanes may be received and then Alignment Markers (AMs) from the plurality of first lanes may be used to determine symbol boundaries and identify the plurality of first lanes. Next, groups of the plurality of first lanes may be de-skewed and checkerboard patterns in the plurality of first lanes may be undone. Then the plurality of first lanes may be symbol-wise multiplexed to a plurality of second lanes. The plurality of second lanes may then be sent.

Symbol multiplexing physical medium attachment (PMA)

Sampling circuitry for receiving an analog signal from photodetector circuitry and generating a sample analog signal. Equalization circuitry for generating an equalized signal comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap. In the equalized signal, amplitudes of the first and second sample values are substantially equal while the third sample values are attenuated relative to the first and second sample values. The first and second sample values correspond with two or more first symbols of a first alphabet. Data slicer and modulo circuitry to generate a data signal based on the equalized signal and perform a modulo operation on the two or more first symbols and to generate one or more second symbols. The second symbols are according to a second alphabet.

Scalable receiver architecture for silicon photonic links

Techniques are provided to provide modified bit sequences generated by the Physical Coding Sublayer (PCS) functional block in a way that considers the subsequent bit-mux operation of the Physical Media Attachment (PMA) sublayer functional block, in order to create symbol sequences for transmission over the physical channels with properties that optimize the performance of the Forward Error Correction (FEC) decoder with error bursts.

Physical coding sublayer with modified bit ordering to improve error burst resiliency

Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.

Component firmware interaction using hardware registers

Techniques and apparatus for optimizing transmitter equalization are described. An example technique includes capturing a single output signal transmitted from a port on at least one channel of a host device. An impulse response of the channel is determined based at least in part on the single output signal. A transmitter feedforward equalization (FFE) is generated, based at least in part on the impulse response of the channel. The transmitter FFE is applied to the channel of the port of the host device.

Transmitter equalization optimization for ethernet chip-to-module (C2M) compliance

Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.

Adaptation of at least one transmit equalizer setting

A method includes transmitting, by a transmitter and over a transmit channel to a remote device, a signal that includes a plurality of signal points and receiving, by a receiver and over a receive channel from the remote device, a response signal that includes a plurality of response points corresponding to the plurality of signal points. The method also includes adjusting the plurality of signal points of the signal until logical values of the plurality of response points invert to produce an adjusted signal, estimating, based on the adjusted signal, a pulse response of the transmit channel, and applying equalization in the transmitter based on the estimated pulse response to reduce an effect of the pulse response on the signal.

Transmitter equalization

Loop timing is performed in a Reconciliation Sublayer (RS) so that the transmit clock frequency can be adjusted to be equal to the receive clock frequency for the entire PHY (including the physical coding sublayer (PCS)). One of two partners is selected to be the timing Slave to the other. If only one partner is capable of loop timing, that partner becomes the Slave. If both partners are capable of loop timing, symmetry breaking can be used to determine which partner should become Slave.

Method and apparatus for synchronous signaling between link partners in a high-speed interconnect

Technologies for cooperative link equalization include a network device with a network interface controller (NIC). The NIC is to monitor variation in a property of a link channel that connects the network device with a target network device. The NIC detects, based on the channel variation, an event that triggers a condition to change an equalization setting of the link channel. In response to the detection, the NIC communicates, via an in-band equalization control channel, changes to the equalization setting of the link channel to the target network device.

Technologies for cooperative link equalization without disruption to link traffic

Technologies for autonegotiation of communications operational modes over copper cable include a network port logic having a communication link coupled to a remote link partner. The network port logic may start an autonegotiation protocol upon reset, when the link is broken, or upon manual renegotiation. The network port logic transmits an autonegotiation page to the remote link partner that indicates single-lane communications ability over copper cable. The network port logic receives an autonegotiation page from the link partner indicating single-lane communications ability over copper cable. If the network port logic and link partner have a common single-lane communication ability, the link may be activated. The autonegotiation pages may be base pages or next pages. The single-lane communication ability may be indicated by one or more bits of the autonegotiation pages. The link may be established at 1 gigabit or 10 gigabits per second. Other embodiments are described and claimed.

Technologies for autonegotiating 10G and 1G serial communications over copper cable

Adaptation of a transmit equalizer using management registers

Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.

Techniques for link partner error reporting

Growing community of inventors

Maayan Baruch, Israel

Adee Ofir Ran