Freescale Semiconductor,inc.

Motorola Corporation

Addi B Mistry

James H Kleffner

David Patten

George F Carney

Daryl R Wilde

Marc Alan Mangrum

Scott K Pozder

Vijay Sarihan

Ziep Tran

Deborah A Hagen

Rina Chowdhury

Rebecca G Cole

Joseph M Haas

Brian H Christensen

Kartik Ananthanarayanan

John Rohde

Edmond Cheng

Jesse Phou

Dennis O Kiffe

John Gehman

A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

Stackable molded packages and methods of making the same

A stacked die system () has a first die () having a first surface with active circuitry, a second die () having a first surface with active circuitry, and a conductive shield () interposed between the first surface of the first die and the first surface of the second die. In one embodiment, the distance between the first surfaces of the first and second die is less than one millimeter. The stacked die system may also include a package substrate () where the active circuitry of the first and second die are electrically connected to the package substrate. The electrical connections may be formed using wire bonds (). Alternatively, the first die may be connected to the package substrate in a flip chip configuration. In one embodiment, the active circuitry of the first die generates RF signals where the shield helps protect the RF signals from interference caused by the active circuitry of the second die.

Digital and RF system and method therefor

A method for testing a semiconductor structure having a set of top-side connections and having a set of bottom-side connections is provided. The method may include providing a device socket for connecting the set of top-side connections and the set of bottom-side connections to a tester. The method may further include providing a device hood for connecting the set of top-side connections to a respective first end of each of a plurality of interconnects in the device hood, wherein a second end of each of the plurality of interconnects in the device hood connects the set of top-side connections to the device socket. The method may further include testing the semiconductor structure using the tester. The semiconductor structure may include at least one integrated circuit to be tested.

Method and apparatus for testing a semiconductor structure having top-side and bottom-side connections

A semiconductor package assembly has an intervening package ( ) that may be connected to a first package ( ) from a first substrate ( ) on a first side of the package ( ) and to a second package ( ) from a second substrate ( ) on a second, opposing side of the package ( ). Electrical contact to a semiconductor die ( ) is made from the first side by wire bonding to wire bond posts ( ) and by balls ( ) from the second side. Electrical contact from one side of the intervening package ( ) to the other may be made by bypassing the die. Electrical contact on either side of the intervening package may be made both within and outside the footprint of the semiconductor die ( ).

Semiconductor package with multiple sides having package contacts

An interconnect structure, such as a flip-chip structure, including a base pad and a stud formed on the base pad and extending from the base pad is disclosed. The stud and base pad are formed to be continuous and of substantially the same electrically conductive base material. Typically, a solder structure is formed on the stud wherein the solder structure is exposed for subsequent reflow attachment to another structure. The present invention relates to packaging integrated circuits, more particularly to the structure and processing of a stud and bump without the standard under bump metallurgy.

Method and apparatus for manufacturing an interconnect structure

A semiconductor device (10) includes a bump structure that reduces stress and thus reduces passivation cracking and silicon cratering that can be a failure mode in semiconductor manufacturing. The stress is reduced by forming a polyimide layer (16) over a passivation layer (14). The polyimide layer (16) is extended beyond an edge of the passivation layer (14) over the metal pad (12). A solder bump (22) is composed of a eutectic material and is formed on the metal pad (12) and on the polyimide layer (16). The polyimide layer (16) prevents the solder bump (22) from contacting the passivation layer (14). This is useful for electroless or electroplating technology and may also be useful in other types of bump forming technology such as C4 and E3.

Method and apparatus for stress relief in solder bump formation on a

A bumped semiconductor device including bond pad (12) formed on a semiconductor die (10), and a passivation layer (14) overlying the semiconductor die and a portion of the bond pad (12). A solder bump (22) is formed so as to overlie the bond pad (12), and a stress isolation trench (15) is formed in the passivation layer (14), so as to surround the solder bump (22).

Bumped semiconductor device having a trench for stress relief

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Austin, TX, United States of America

Addi B Mistry