Magic Technologies, Inc.

Other

Applied Materials, Inc.

Headway Technologies, Incorporated

Adam Zhong

Chyu-Jiuh Torng

Tom Zhong

Wai-Ming Johnson Kan

Rongfu Xiao

Daniel H Liu

Atul D Ayer

Thomas H Osterheld

Gopalakrishna B Prabhu

Gregory E Menk

Garlen C Leung

Evangeline Cruz

Christopher Heung-Gyun Lee

Noymi Yam

Peter McReynolds

Padmanabh Bhatt

Terry Kin Ting Ko

Vasanth N Mohan

Yi-Yung Tao

The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a 'super-flat' interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.

Method of high density memory fabrication

A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

High density spin-transfer torque MRAM process

A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions.

Method of magnetic tunneling layer processes for spin-transfer torque MRAM

A process is described for making contact to the buried capping layers of GMR and MTJ devices without the need to form and fill via holes. CMP is applied to the structure in three steps: (1) conventional CMP (2) a Highly Selective Slurry (HSS) is substituted for the conventional slurry to just expose the capping layer, and (3) the HSS is diluted and used to clean the surface as well as to cause a slight protrusion of the capping layers above the surrounding dielectric surface, making it easier the contact them without damaging the devices below.

Use of CMP to contact a MTJ structure without forming a via

Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level to form a field induced MRAM device. The memory portion of the device includes N parallel word lines, which may be clad, overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the N&#xd7;M intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the N&#xd7;M electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level. Of particular importance are process steps that replace single damascene formations by dual damascene formations, different process steps for the formation of clad and unclad word lines and the formation of patterned electrodes for the memory cells prior to the patterning of the cells themselves.

Method of high density field induced MRAM process

An MTJ pattern layout for a memory device is disclosed that includes two CMP assist features outside active MTJ device blocks. A first plurality of dummy MTJ devices is located in two dummy bands formed around an active MTJ device block. The inner dummy band is separated from the outer dummy band by the MTJ ILD layer and has a MTJ device density essentially the same as the MTJ device block. The outer dummy band has a MTJ device density at least 10% greater than the inner dummy band. The inner dummy band serves to minimize CMP edge effect in the MTJ device block while the outer dummy band improves planarization. A second plurality of dummy MTJ devices is employed in contact pads outside the outer dummy band and is formed between a WL ILD layer and a BIT ILD layer thereby minimizing delamination of the MTJ ILD layer.

Method of magnetic tunneling junction pattern layout for magnetic random access memory

Methods and compositions are provided for planarizing a substrate surface with reduced or minimal topographical defect formation during a polishing process for dielectric materials. In one aspect a method is provided for polishing a substrate containing two or more dielectric layers, such as silicon oxide, silicon nitride, silicon oxynitride, with at least one processing step using a fixed-abrasive polishing article as a polishing article. The processing steps may be used to remove all, substantially all, or a portion of the one or more dielectric layers, which may include removal of the topography, the bulk dielectric, or residual dielectric material of a dielectric layer in two or more steps.

Polishing processes for shallow trench isolation substrates

Dosage forms and methods for the controlled release of antidepressives, such as exemplified by phenoxyethyl substituted-1,2,4-triazolones, as a suspension or a slurry over a prolonged period of time are described.

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Milpitas, CA, United States of America

Adam Zhong