Intel Corporation

Lntel Corporation

Adam T Lake

Prasoonkumar Surti

Abhishek R Appu

Carl S Marshall

Altug Koker

Joydeep Ray

Jeffery S Boles

John H Feit

Subramaniam M Maiyuran

Balaji Vembu

Travis T Schluessler

Karthik Vaidyanathan

Kai Xiao

Nikos Kaburlasos

Deepak Shashidhar Vembar

Devan Burke

Elmoustapha Ould-Ahmed-Vall

Kamal Sinha

Michael Apodaca

Hugues Labbe

Wenyin Fu

Chandrasekaran Sakthivel

Narayan Srinivasa

Justin E Gottschlich

Ankur N Shah

Feng Chen

Eriko Nurvitadhi

Linda L Hurd

Sara S Baghsorkhi

Ben J Ashbaugh

Nicolas C Galoppo Von Borries

Rajkishore Barik

Dukhwan Kim

Nadathur Rajagopalan Satish

James M Holland

Tsung-Han Lin

Jacek Kwiatkowski

Josh B Mastronarde

Jonathan Kennedy

Farshad Akhbari

Jill MacDonald Boyce

Vasanth Ranganathan

Tomer Bar-On

Atsuo Kuwahara

Brent E Insko

Radhakrishnan Venkataraman

Varghese George

Murali Ramadoss

Scott R Janus

Carsten Benthin

Peter L Doyle

Selvakumar Panneer

Karthik Veeramani

Guei-Yuan Lueh

Lidong Xu

Gabor Liktor

Philip R Laws

Anupreet S Kalra

Kun Tian

Vallabhajosyula S Somayazulu

Narayan Biswal

Ingo Wald

Daniel Pohl

Stanley J Baran

Mike MacPherson

Pattabhiraman K

Bhushan M Borole

Gokcen Cilingir

Nilesh V Shah

Barnan Das

David J Cowperthwaite

Sameer Kp

Archie Sharma

David M Cimini

Louis Feng

Mayuresh M Varerkar

Michael D Rosenzweig

Eric J Hoekstra

Sayan Lahiri

Johannes Guenther

Sherine Abdelhak

Zhijun Lei

Slawomir Grajewski

Glen J Anderson

Christopher J Hughes

Eric C Samson

David M Puffer

Stephen Junkins

Brian T Lewis

Rahul P Sathe

Nilesh K Jain

Michael Mesnier

Soethiha Soe

Daniel D Johnston

Zhi Hu Wang

Tomas G Akenine-Moller

Zhi Jun Wang

Sven Woop

John G Gierach

Michael Doyle

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

Systolic arithmetic on sparse data

One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

Graphics architecture including a neural network pipeline

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Motion biased foveated renderer

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

Data locality enhancement for graphics processing units

Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.

Apparatus and method for efficient graphics processing including ray tracing

One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

Apparatus and method for foveated rendering, bin comparison and TBIMR memory-backed storage for virtual reality implementations

Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.

Sensory enhanced augmented reality and virtual reality device

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Order independent asynchronous compute and streaming for graphics

One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.

An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.

Growing community of inventors

Portland, OR, United States of America

Adam T Lake