Lsi Logic Corporation

Lsi Corporation

Adam S Browen

Craig R Chafin

David W So

Jeffrey K Whitt

Erik Paulsen

Carl Edward Gygi

William J Schmitz

Andrew Hadley

Stuart L Nuffer

Jeffery K Whitt

John Grabarek

Steve A Olson

Methods and apparatus are provided for burst transfers of data between DDR memories and embedded processors during training of the PHY interface in an embedded system. An embedded system comprises an embedded processor having at least one cache controller; a memory, wherein the memory has an atomic memory access that comprises a plurality of clock edges; and a memory controller having a physical interface to convert digital signals between the embedded processor and the memory, wherein the cache controller executes a training process to determine a delay through the physical interface for each of the plurality of clock edges using a burst transfer of data. The burst transfer comprises reading a data pattern from the memory and storing the data pattern in one or more registers in the embedded processor.

Methods and apparatus for burst data transfers between double data rate (DDR) memories and embedded processors during training

An apparatus and a method for analyzing signals within an integrated circuit are described. In one embodiment of the present invention, internal IC signals are tapped, sampled and stored according to one or more sampling criteria. The signals may be taken from multiple locations within the IC and the information stored may include data, timing information, control data and other such information related to the tapped signals. The stored information may be provided to an external device for analysis.

Dynamic on-chip logic analysis

An improved PCI-X verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI-X system. One or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values. In one aspect, an apparatus and method for testing a PCI-X device for compliance under the PCI-X Addendum to the PCI Local Bus Specification in completer operation are provided. In another aspect, an apparatus and method for testing a PCI-X-device for compliance under the PCI-X addendum to the PCI Local Bus Specification in requester operation are provided.

PCI-X bus system testing and verification apparatus and method

An improved PCI verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI system. One or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values. In one aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in target operation is provided. In another aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in master operation is provided.

PCI bus system testing and verification apparatus and method

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Colorado Springs, CO, United States of America

Adam S Browen