Topside Research, LLC

Adam Rappoport

Chris Haywood

Thomas C Reiner

Heath Stewart

Michael J De La Garrigue

Bao K Vuong

Nadim Shaikli

Ken Wong

Phil Terry

Kirk Jong

Neely Walls

Mike De La Garrigue

A network processor having bypass capability in which some data units are diverted from being processed by the processor core of the network processor. In one embodiment, a network processor may include a receiver to receive data units, configuration information used to evaluate whether the data units require processing, a processor core to process data units that require processing, a bypass store to hold those data units which do not require processing by the processor core, and a transmitter to transmit the data units. In one embodiment, a method may include receiving a plurality of data units, receiving configuration information, evaluating whether each of the data units requires processing based on the configuration information, bypassing processing those of the data units that do not require processing based on the evaluating, processing those of the data units that require processing based on the evaluating, and transmitting the data units.

Network processor having bypass capability

There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Optimized switching method

Switch for bus optimization

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Agoura Hills, CA, United States of America

Adam Rappoport