International Business Machines Corporation

Globalfoundries Inc.

Adam P Matheny

Jose Luis Neves

Alice Hwajin Lee

David J Widiger

Lewis William Dewey, Iii

Susan Elizabeth Cellier

Anthony D Hagin

Ronald Dennis Rose

Markus Buehler

James J Curtin

Douglas S Search

Jesse Peter Surprise

Gerald Strevig, Iii

Charles Kyriakos Vakirtzis

Dhaval R Sejpal

Moussadek Belaidi

Bryan A Meyer

Kerim Kalafala

Christopher J Berry

Michael H Wood

Robert J Allen

Paul David Kartschoke

Gregory M Schaeffer

Louise Helen Trevillyan

Michael Alexander Bowen

Pooja M Kotecha

Tsz-mei Ko

Ravichander Ledalla

Chris Aaron Cavitt

Ruchir Puri

Paul Gerard Villarrubia

Gustavo Enrique Tellez

Lakshmi Narasimha Reddy

David S Wolpert

Alexander Joel Suess

Nathaniel Douglas Hieter

Patrick M Williams

Robert Mahlon Averill, Iii

Michael Kazda

Rama Gopal Gandham

Shawn Kollesar

Mitchell R DeHond

Jose Luis Pontes Correia Neves

Amanda Christine Venton

Douglas Keller

Paul M Campbell

Joseph Koone

Smitha Reddy

Ron D Rose

Jose Luis Pontes Neves

Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

Cross-hierarchy antenna condition verification

Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.

Noise impact on function (NIOF) reduction for integrated circuit design

Aspects of the invention include generating a set of via mesh specifications for a cell within an integrated circuit. Each via mesh specification defines one or more straps on each layer above a first layer, which includes one or more pins that form a pin terminal, to a top layer that connects the cell to a net for interconnection of the cell with one or more other cells, and also one or more vias that interconnect adjacent ones of the layers. Aspects also include verifying whether each via mesh specification is a universally routable via mesh specification guaranteeing that the cell interconnects with other cells through the net while meeting all design rules, and including only the via mesh specifications of the set of via mesh specifications that are universally routable in a library of via mesh specifications. The library is used to finalize and fabricate the integrated circuit.

Generation and selection of universally routable via mesh specifications in an integrated circuit

Techniques for noise impact on function (NIOF) reduction for an integrated circuit (IC) design are described herein. An aspect includes receiving a list of victim nets in which NIOF failures are present in an IC design. Another aspect includes attempting NIOF correction in each victim net of the list of victim nets. Another aspect includes, based on a failure of a NIOF correction in at least one victim net of the list of victim nets, saving the at least one victim net to a wire promote/demote list. Another aspect includes updating the list of victim nets based on the NIOF correction. Another aspect includes, based on determining that the updated list of victim nets is empty, promoting or demoting the at least one victim net from the wire promote/demote list in the IC design.

Techniques for net routing for an integrated circuit (IC) design are described herein. An aspect includes receiving a netlist corresponding to a net in an IC design. Another aspect includes identifying intermediate logic in the net, wherein the intermediate logic is connected between a source and a sink of the net, and wherein the sink is located downstream from the source in the IC design. Another aspect includes hiding the intermediate logic from the netlist. Another aspect includes creating a global route in the IC design between the source and the sink of the net without the intermediate logic. Another aspect includes restoring the intermediate logic to the netlist. Another aspect includes placing the intermediate logic along the global route.

Net routing for integrated circuit (IC) design

Methods, systems and computer program products for improved placement of a clock gating latch are provided. Aspects include identifying a clock gating latch that is designated to control a local clock buffer. Aspects also include determining a plurality of data latches that are designated to be controlled by the local clock buffer. Aspects also include determining positions of the plurality of data latches within a layout. Aspects also include determining a position of the clock gating latch within the layout based on the positions of the plurality of data latches within the layout.

Clock gating latch placement

Techniques for logic partition reporting for an integrated circuit (IC) design are described herein. An aspect includes generating a physical domain representation of an IC design based on a logic domain representation that includes a plurality of logic partitions, the physical domain representation including a plurality of logic clusters, each corresponding to a respective logic partition. Another aspect includes assigning a logic partition identifier corresponding to a logic partition of the plurality of logic partitions to each IC element in the physical domain representation. Another aspect includes assigning a pin name to each of the plurality of pins corresponding to the plurality of IC elements, wherein a pin name is derived based on the logic partition identifier of the IC element associated with the pin. Another aspect includes generating a timing report for a logic cluster based on the logic partition identifiers and the pin names.

Logic partition reporting for integrated circuit design

Techniques for an IC design include placing latches between a source and one or more sinks in the IC design, and performing an iterative process for maximizing slack on one or more input nets and one or more output nets for each of the latches, minimizing an absolute difference of the slack. The IC design includes optimizing routing for the latches and placing a clock gating latch in the IC design designated to control a LCB of LCBs. The IC design includes placing LCB logic in the IC design to control a required number of the LCBs, and placing a local clock buffer controller in the IC design in proximity to the positions of the latches.

Single-bit latch optimization for integrated circuit (IC) design

Techniques for logic partition identifiers for an integrated circuit (IC) design are described herein. An aspect includes receiving a logic domain representation of an IC design comprising a plurality of logic partitions each comprising a respective plurality of IC elements. Another aspect includes generating a physical domain representation of the IC design based on the logic domain representation comprising a plurality of logic clusters each corresponding to a respective logic partition, wherein each of the plurality of logic clusters comprises a respective plurality of IC elements. Another aspect includes assigning a logic partition identifier to each IC element in the physical domain representation, wherein the logic partition identifier of an IC element corresponds to a logic partition. Another aspect includes determining timing information for a logic partition based on the logic partition identifiers of the plurality of IC elements of a logic cluster associated with the logic partition.

Logic partition identifiers for integrated circuit design

Techniques for latches include ordering latches by connectivity from a source to sinks. An iterative process is performed which includes selecting a selected latch in the connectivity, drawing a bounding box around the selected latch to encompass input nets and output nets, and using a two-dimensional optimizer to find a new placement location for selected latch by solving for optimization criteria. The optimization criteria includes maximizing slack on the input and output nets of the selected latch, minimizing an absolute difference of the slack between the input output nets, and identifying the new placement location within the bounding box that balances maximizing the slack on input and output nets versus minimizing the absolute difference of the slack between input nets and output nets. The current location of the selected latch is updated between the source and sinks to be the new placement location identified in the bounding box.

Multi-fanout latch placement optimization for integrated circuit (IC) design

Techniques for parallel power down processing of an integrated circuit (IC) design are described herein. An aspect includes receiving IC design information comprising a plurality of IC elements. Another aspect includes identifying a plurality of timing endpoints in the IC design information. Another aspect includes determining a plurality of nets, each net comprising a respective subset of the plurality of IC elements, based on the identified plurality of timing endpoints. Another aspect includes performing power down processing of net drivers in the plurality of nets, wherein the power down processing of at least a subset of the plurality of nets is performed in parallel.

Parallel power down processing of integrated circuit design

A computer-implemented method for extracting a capacitance for a target wire of an integrated circuit includes receiving a design of the integrated circuit having a plurality of wiring layers and selecting a target wire to perform the capacitance extraction. The method further includes determining a first adjacent wiring layer and a second adjacent wiring layer and removing a first subset and a second subset of a plurality of non-adjacent wiring layers from the plurality of wiring layers. The method includes approximating a first plate to be used in the extraction based on the first subset of the plurality of non-adjacent wiring layers and approximating a second plate to be used in the extraction based on the second subset of the plurality of non-adjacent wiring layers and performing the extraction of the target wire based on the first and second adjacent wiring layers and the first and second plates.

Method for improving capacitance extraction performance by approximating the effect of distant shapes

Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Process for improving capacitance extraction performance

Methods are disclosed to determine if wiring resources are available in the neighborhood of a physically routed net in all three dimensions. Such a method can select a wire trait based on an amount of usage of each wire segment in the net and the total percentage usage of the net. The method can also re-route a net using new wiring resources after determining that wiring resources are available. The new resources can provide improved RC (delay) characteristics and reduced signal coupling. The method can be applied to a VLSI design with multiple fails.

Resource aware method for optimizing wires for slew, slack, or noise

An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

Incremental parasitic extraction for coupled timing and power optimization

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Beacon, NY, United States of America

Adam P Matheny