Xilinx, Inc.

Adam P Donlin

Bernard J New

Kyle Corbett

Patrick Lysaght

Brandon Blodget

Stephen M Trimberger

Julian M Kain

Prasanna Sundararajan

Khang Kim Dao

Paul M Hartke

Christopher J Case

Paul R Schumacher

Nabeel Shirazi

Shay Ping Seng

Jeffrey H Seltzer

Amit Kasat

Srinivas Beeravolu

Tobias J Becker

Lizhi Hou

Biping Wu

Xiaoyang Zhang

Hayden Kwok-Hay So

Douglas M Densmore

Control of a reconfigurable platform can include determining, by a host computer, an interface universally unique identifier (UUID) of an interface of platform circuitry implemented on an accelerator, wherein the accelerator is communicatively linked to the host computer. An electronic request to run a partition design on the accelerator is received by the host computer. In response to the electronic request, the host computer determines an interface UUID for an interface of the partition design and determines compatibility of the partition design with the platform circuitry based on a comparison of the interface UUID of the partition design with the interface UUID of the platform circuitry. The partition design is implemented on the accelerator in response to determining that the partition design is compatible with the platform circuitry.

Flexible data-driven software control of reconfigurable platforms

Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.

Scalable scribe regions for implementing user circuit designs in an integrated circuit using dynamic function exchange

Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel can be determined. An interconnect architecture for the dynamic design can be constructed based on the global resource used by the first kernel.

Adaptable dynamic region for hardware acceleration

Approaches for verifying connectivity of signals in a circuit design include generating a configured version of the circuit design based on input parameter values. The configured version specifies connections from source pins of ports of circuit blocks of the configured version to destination pins of ports of circuit blocks. Expected source-destination connections between source pins and destination pins of the ports of the circuit blocks of the configured version are determined from the input parameter values. A connectivity checker that includes HDL code is generated based on the expected source-destination connections. For each of the expected source-destination connections, the HDL code forces a first signal value on a source pin of the expected source-destination connection in the configured version of the circuit design and determines whether or not a second signal value at a destination pin of the expected source-destination connection matches the first signal value.

Verification of connectivity of signals in a circuit design

Approaches are disclosed for testing a module of a circuit design. The module is simulated a first time using a testbench on a programmed processor. Event data is captured to a first file during the simulating. For each event, the event data describes a signal identifier, an associated signal value, and an associated timestamp. The event data of the first file is transformed into a hardware description language (HDL) replay module.

Generation of a replay module for simulation of a circuit design

Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

System level circuit design

Approaches for preparing a system that is reconfigurable to implement a plurality of optional hardware functions are disclosed. In one approach, a method includes simulating the operation of the system during a time interval. The system is reconfigurable to implement a subset of the optional hardware functions, and the simulating determines which of the optional hardware functions are active and which of the optional hardware functions are inactive during a plurality of subintervals of the time interval. Respective circuit resource sets are estimated for the subintervals of the time interval. For each of the subintervals, the respective circuit resource set implements the system including the optional hardware functions that are active during the subinterval. Information describing the respective circuit resource sets for the subintervals is stored for preparing partial reconfigurations of the system.

Analysis of the operation of a reconfigurable system

A security circuit for a reprogrammable logic IC includes an evolved circuit that ties the performance of the security circuit to the physical properties of that particular reprogrammable logic IC. The security circuit can be a decryption and/or encryption circuit that decrypts and/or encrypts, respectively, a configuration bitstream for the IC. Because of the link between the performance of the security circuit and the physical properties of the IC, the security circuit cannot be used in other ICs. For example, an encrypted bitstream that can be decrypted by the security circuit in a first IC will typically not be decrypted by the same security circuit in a second IC, since the physical properties of the two ICs will typically be different. The evolved circuit can comprise a portion of the security circuit, such as a security key generator, or it can comprise the full security circuit.

Evolved circuits for bitstream protection

A top-level directory of a virtual file system is created. A hierarchy of directories is created under the top-level directory including creating a first file that contains an architecture description of the multi-device circuit arrangement. The directories have names indicative of the plurality of devices and configurable resources of the plurality of devices of the architecture description specified in the first file. A first set of one or more files is created that contain state data or configuration data for configuring resources of the plurality of devices to perform functions specified by the configuration data. A mapping of the configuration data to the resources of the plurality of devices is determined, and configuration data is stored in the configurable resources according to the mapping.

Configuration of a large-scale reconfigurable computing arrangement using a virtual file system interface

Approaches for reporting hardware events from circuitry implemented in an integrated circuit (IC). The IC is configured with a circuit to be analyzed and an event monitor circuit. A process invokes an application programming interface (API) function that references an operating system managed object. The API function includes a parameter value that references the object. The process is operated in a first manner when the object is in a first state. An interrupt signal is generated by the event monitor circuit to the processor in response to an input signal from the circuit under analysis, which initiates execution of an interrupt handler. The object is placed in a second state by the interrupt handler. The process is operated in a second manner different from the first manner in response to the object transitioning to the second state.

Programmable hardware event reporting

Approaches for managing a simulation model. A processor-implemented method includes simulating an electronic system using the simulation model and a simulator. The simulation model includes an assertion test that has an associated limit. The simulator counts a number of times the assertion test is evaluated during simulation, which is the evaluation count. When the simulator determines that the evaluation count has reached the limit, the simulation is stopped.

Self-disabling simulation models using limits on assertions

A method and system are disclosed. The system includes a trusted loader. The method includes downloading an IP core from a vendor to a target device. The IP core is received in an encrypted form at the target device, which can be, for example, a programmable logic device.

Secure exchange of IP cores

Various approaches for controlling a circuit implemented on an integrated circuit device having programmable logic. According to one approach a hierarchy of directories and files are maintained in a virtual file system that is registered with an operating system. The directories and files are associated with resources of the programmable logic. Each file represents a respective data set of configuration data for an associated one of the resources, and at least one of the files is a clock control file that is associated with a clock control circuit on the integrated circuit. A first value is stored in the clock control circuit of the programmable logic in response to invocation of an operating system file access command that references the clock control file and specifies the first value. Advancement of a clock signal on the programmable logic is controlled in response to the first value stored in the clock control circuit.

Debugging using a virtual file system interface

A computer-implemented method of incorporating probe points within a circuit design for implementation within an integrated circuit device can include routing probe nets of the circuit design in an overlap mode, identifying a plurality of probe net routes including a common overlapping portion, and including a switch at each location within the circuit design where at least two probe net routes of the plurality of probe net routes diverge from a common point. The circuit design can be output.

Growing community of inventors

Los Gatos, CA, United States of America

Adam P Donlin