Bae Systems Information and Electronic Systems Integration Inc.

Ovonyx Inc.

Integrated Device Technology, Inc.

Bae Systems Information and Electronics Systems Integration Inc.

Adam Matthew Bumgarner

Bin Li

Daniel Pirkl

Gustavo James Mehas

Nicholaus Wayne Smith

Nadim F Haddad

Neil Edward Wood

Scott Doyle

Shankarnarayana Ramaswamy

George Michael

Wayne Neiderer

Tri-Minh Hoang

A wireless power transmitter may include a bridge inverter and a plurality of parallel paths operably coupled to the bridge inverter. Each path includes a resonance tank including a transmit coil coupled with at least one resonance capacitor, a first switch serially coupled with the resonance tank and switching node A of the bridge inverter, a first clamping element in parallel with the first switch, a second switch serially coupled with the resonance tank and switching node B of the bridge inverter, and a second clamping element in parallel with the second switch. A method includes generating a wireless power signal through a used coil in a first parallel path, and clamping a parasitic voltage generated in at least one unused coil in at least one additional parallel path through a clamp element across a switch in the at least one parallel path for the at least one unused coil.

Apparatuses and wireless power transmitters having multiple transmit coils and related method

An adjustable write pulse generator is disclosed. The adjustable write pulse generator includes a band-gap reference current, a programmable ring oscillator, a frequency divider and a single pulse generator. The band-gap reference current circuit generates a well-compensated current over a predetermined range of temperatures needed to program a chalcogenide memory cell. The programmable ring oscillator generates a first set of continuous write '0' and write '1' pulse signals based on the well-compensated current. The frequency divider then divides the first set of continuous write &#x201c;0&#x201d; and write &#x201c;1&#x201d; pulse signals into a second set of continuous write &#x201c;0&#x201d; and write &#x201c;1&#x201d; pulse signals. The single pulse generator subsequently converts the second set of continuous write &#x201c;0&#x201d; and write &#x201c;1&#x201d; pulse signals into a single write &#x201c;0&#x201d; pulse signal or a single write &#x201c;1&#x201d; pulse signal when programming the chalcogenide memory cell.

Adjustable write pulse generator within a chalcogenide memory device

An analog access circuit for characterizing chalcogenide memory cells is disclosed. The analog access circuit includes an analog access control module, an address and data control module, and an analog cell access and current monitoring module. The analog access control module selectively controls whether a normal memory access or an analog memory access should be performed on a specific chalcogenide memory cell. The address and data control module allows a normal memory access to the chalcogenide memory cell according to an input address. The analog cell access and current monitoring module performs an analog memory access to the chalcogenide memory cell according to the input address, and monitors a reference current from a sense amplifier associated with the chalcogenide memory cell.

Analog access circuit for validating chalcogenide memory cells

A read reference circuit for a sense amplifier within a chalcogenide memory device is disclosed. The read reference circuit provides a reference voltage level to the sense amplifier for distinguishing between a logical '0' state and a logical '1' state within a chalcogenide memory cell. In conjunction with a precharge circuit, the read reference circuit generates a selectable read reference current to the sense amplifier in order to detect the logical state of the chalcogenide memory cell. The precharge circuit precharges the bitlines of the chalcogenide memory cell before the sense amplifier detects the logical state of the chalcogenide memory cell.

Read reference circuit for a sense amplifier within a chalcogenide memory device

A method for connecting circuit elements within an integrated circuit for reducing single-event upsets is disclosed. The integrated circuit includes a first and second circuit elements that are substantially identical to each other. In order to reduce the single-event upsets to the first and second circuit elements, each of the first and second circuit elements is divided into a first sub-element and a second sub-element. The first sub-element of the first circuit element is connected to the second sub-element of the second circuit element. The second sub-element of the first circuit element is connected to the first sub-element of the second circuit element. As a result, the nodal spacings between the sub-elements within the first and second circuit elements are effectively increased without demanding additional real estate.

Method for connecting circuit elements within an integrated circuit for reducing single-event upsets

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Duluth, GA, United States of America

Adam Matthew Bumgarner