Allegro Microsystems, LLC

Voxtel, Inc.

Teledyne Scientific and Imaging, LLC

Teledyne Licensing, LLC

Ladarsystems, Inc.

Adam Lee

George M Williams

Charles Myers

Shunming Sun

Jehyuk Rhee

Stefan Clemens Lauxtermann

John C Stevens

Brent R Jensen

Atul Joshi

Andrew S Huntington

Leo Filippini

Methods and apparatus for a detector system having a photodetector and an amplifier to amplify the photodetector signal. A discriminator generates an active output signal when the output from the amplifier is greater than a threshold. An injection circuit is coupled to the input of the amplifier. The injection circuit is configured to selectively inject a test pulse that mimics a pulse from the photodetector for verifying operation of the detector system.

Programmable active pixel test injection

Systems, methods, and circuits provide delay-locked loop (DLL) timing error mitigation. A DLL false-lock detection system can include DLL circuitry configured to receive a reference clock signal having a time period. The system can include shift register circuitry and latched comparison circuitry which can determine a time period of a locked condition of the DLL delay line with respect to the reference clock signal time period. The system can determine whether the system is correctly locked to the base time period or incorrectly locked to a multiple of the base time period. A further system can operate to cause a phase detector circuitry in a DLL to ignore the first edge of a reference clock signal presented to the phase detector circuitry and thereby avoid stuck-lock conditions.

Delay-locked-loop timing error mitigation

Methods and apparatus for an arrayed time to digital converter (TDC) having matched delay line sampling. In embodiments, a TDC includes a coarse counter circuit to provide an event coarse timing measurement for an event, a coarse counter delivery network to deliver a count value in the coarse counter circuit to a memory storage element circuit, and an array of matched delay lines to provide an event fine timing measurement to the memory storage element circuit. An array of event sample signal generators can generate signals for the event and an array of encoders can encode fine timing measurement information from the memory storage element circuit, where an output of the encoder and the event coarse timing measurement information provide a timestamp for the event. A global delay-locked loop can incorporate a matched delay line coupled to the array of matched delay lines.

Arrayed time to digital converter

Methods and apparatus for nonuniformity correction (NUC) for a sensor having an avalanche photodiode (APD) array and an integrated circuit. The sensor can include anode bias control module, a passive mode module, and an active mode module. DC photocurrent from the APD array can be measured and used for controlling an anode reverse bias voltage to each element in the APD to achieve a nonuniformity correction level less than a selected threshold.

Non-uniformity correction of photodetector arrays

An imaging device in accordance with the present disclosure comprises of a pixelated array of semiconductor detector elements, each of the pixels in the array having an in-pixel integrated circuit, the integrated circuit having a comparator, a readout decoder block, and an address arbitration control block. The readout decoder block reads out the integrated signals of the pixels. The address arbitration control block determines the pixel address of the pixels charging beyond a threshold voltage, the threshold exceedance determined by the comparator. The addressed pixels are provided a timestamp for each of the pixels integrating beyond the threshold voltage, the timestamp provided by an off-pixel time-to-digital converter (TDC), the value of the timestamp corresponding with the accumulated charge of the pixel.

High dynamic range image sensor

An imaging device is disclosed, the device comprising a pixelated array of semiconductor detector elements, in which each detecting element is electrically connected to an integrated circuit, the integrated circuit comprising a passive signal path and an active signal path. The active path provides consecutive frame imaging and the active path detects the location of transient events. The device further comprising a readout decoder block, the readout decoder block controlling operation of the passive paths. Additionally the device comprises of an address arbitration control block, the address arbitration control block controlling operation of the active paths, wherein the address arbitration control block readout of the active paths is independent of readout of the passive paths.

Event tracking imager

An imaging device comprises of a pixelated array of semiconductor detector elements, in which each detecting element is electrically connected to an integrated circuit, the integrated circuit of each of the pixels comprising a passive signal path and a transient signal path. The passive path provides consecutive frame or scene imaging and the transient path detects the transient electromagnetic events such as laser pulses. The transient path is electrically connected to a timing circuit, the timing circuit for determining the time-of-flight of return pulses emitted from the electromagnetic source detected by the transient signal paths. Wherein the passive path and transient path operate simultaneously enabling simultaneous passive and LADAR imaging.

Asynchronous LADAR and imaging array

A 3D stacked electro-optical radiation imaging device with a plurality of integrated circuit layers, the device having a pixelated array of semiconductor detector elements, in which each detecting element is electrically connected a stacked integrated circuit. The stacked integrated circuit has a mixed signal layer and a reconfigurable layer. The mixed signal layer has a passive signal path and an active signal path. A readout decoder block controls operation of the passive paths. The active signal path triggers readout upon transient event detection and is readout by an address arbitration control block, the address arbitration control block operating independent and asynchronous to the readout of the passive path and transient event detection initiates the identification of the location of and readout of the signaling active path. The reconfigurable layer has processing units that each correspond to one or more pixels in the pixelated array. The processing units are reconfigurable through received signals from either the passive path, the active path, or an external signal. A controller programs and communicates with the mixed signal layer and reconfigurable layer

Reconfigurable asynchronous readout array

An imaging device is disclosed, the device comprising a pixelated array of semiconductor elements, in which each detecting element is electrically connected to an integrated circuit, the integrated circuit comprising a passive signal path and an active signal path. The passive path provides consecutive frame imaging and the active path detects the location of transient events. The device further comprising a readout decoder block, the readout decoder block controlling operation of the passive paths. Additionally, the device comprises of an address arbitration control block, the address arbitration control block controlling operation of the active paths, wherein the address arbitration control block readout of the active paths are independent of readout of the integrated signal readout from the passive paths.

Asynchronous readout array

A correlated double sampling circuit and method for providing the same are disclosed. The circuit may include an amplifier, a plurality of capacitors, and a switch matrix. The amplifier provides a reset voltage replica and a signal voltage replica. The switch matrix controls a plurality of switches to perform correlated double sampling over at least three phases. The first phase for sampling the reset voltage replica on a first and second capacitors. The second phase for sampling the reset voltage replica and the kTC noise on a third capacitor. The first phase producing a thermal kTC noise from the first and second capacitors. The third phase for subtracting a charge representing the signal voltage replica, the kTC noise and the reset voltage replica, combined, from the charge sampled in the second phase to provide an output voltage. The method for providing low noise correlated double sampling includes controlling the plurality of switches to provide the at least three phases.

Low noise correlated double sampling amplifier for 4T technology

An imaging system includes a row and column array of active pixels, each having an associated pitch. In response to respective control signals, each pixel outputs a reset level which includes noise components, or a signal level which includes signal and noise components. Multiple column buffers, each having a pitch equal to or less than that of a pixel, convey the outputs of respective pixel columns to a bus line. Each buffer comprises 'odd' and 'even' S&H/CDS circuits, which process the pixel outputs of odd and even rows, respectively. Each S&H/CDS circuit subtracts pixel reset level from signal level to produce an output in which correlated noise is suppressed. Each column buffer includes a buffer amplifier which conveys the output to the bus line. A gain amplifier separate from the column buffers is coupled to the bus line such that it amplifies the outputs of a multiple column buffers.

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Portland, OR, United States of America

Adam Lee