Micron Technology Incorporated

Dow Global Technolgoies LLC

Rohm & Haas Electronic Materials LLC

Lodestar Licensing Group LLC

Adam L Olson

William R Brown

Kaveri Jain

Ho Seop Eom

David A Kewley

Lijing Gou

Xue Chen

Anton J deVillers

Rohit Kothari

Jason Reece

Nicholas Hendricks

Scott Schuldenfrei

Jason C McFarland

John David Hopkins

Scott E Sills

Lifang Xu

Paul D Shirley

Matthew Park

Yoshiki Hishiro

Xiaosong Zhang

Robert Dembi

Lance Williamson

Jeslin J Wu

Hiroyuki Mori

Troy V Gugel

Bo Zhao

Xue (Gloria) Chen

Tien Minh Quan Tran

Peter Trefonas, Iii

Dan B Millward

Phillip Dene Hustad

Nancy M Lomeli

Jong Keun Park

Merri Lyn Carlson

Nik Mirin

Christopher Nam Lee

Chao Zhu

Md Zakir Ullah

Kok Siak Tang

Jixin Yu

Mohammad Moydul Islam

Zhigang Yang

Hui Chin Chong

Yoshiaki Fukuzumi

Justin B Dorhout

Richard J Hill

Matthew J King

Lars P Heineck

Harsh Narendrakumar Jain

Naveen Kaushik

Shruthi Kumara Vadivel

Biow Hiem Ong

Martin Jared Barclay

Joel D Peterson

Michael J Gossman

Kah Sing Chooi

Zhen Feng Yow

A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

Microelectronic devices including stadium structures

A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.

Methods of forming nanostructures including metal oxides using block copolymer materials

A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

Semiconductor devices comprising steps

An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

Electronic devices comprising multilevel bitlines, and related methods and systems

Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.

Methods of forming a staircase structure

Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

Microelectronic devices with tiered decks of aligned pillars exhibiting bending and related methods

A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

Microelectronic devices and related methods of forming microelectronic devices

Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, 'pillar density' being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

Microelectronic devices with tiered decks of differing pillar density and related methods and systems

Self-assembled nanostructures including metal oxides and semiconductor structures comprised thereof

Methods of forming microelectronic devices, and related microelectronic devices, and electronic systems

Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

Apparatus comprising staircase structures

Methods of forming a semiconductor device

Methods of improving adhesion of photoresist in a staircase structure and methods of forming a staircase structure

Growing community of inventors

Boise, ID, United States of America

Adam L Olson