Micron Technology Incorporated

Adam J Hieb

Preston Allen Thomson

Kevin Roy Brandt

Jonathan Tanguy

Matthew David Rowley

Sanjay Tiwari

Robert W Strong

Todd A Marquart

Andrew M Kowles

Tyler L Betz

Adam C Guy

A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.

Data erase operations for a memory system

A system includes a memory device and a processing device coupled to the memory device. The memory processing device can perform operations including receiving data indicative of occurrence of a plurality of events. The processing device can perform operations including determining an event log type for each of the plurality of events. The processing device can perform operations including storing an identifier associated with each of the determined event log types. The processing device can perform operations including updating a counter value associated with each identifier in response to occurrence of an event associated with the respective identifier.

Memory sub-system event log management

A system includes a memory component and a processing device, operatively coupled with the memory component, to generate a physical presence security identification (PSID) for the memory component using a statistically random number generator. The processing device, operatively coupled with the memory component, can securely retrieve the PSID and revert the memory component to an original state using the PSID.

Memory physical presence security identification

A method includes enabling a manufacturing mode at least partially based on a first signal provided via one of a number of reserved pins of an interface connector. The method can further include providing, in response to enabling the manufacturing mode, a second signal to a memory component coupled to the interface connector via a number of other pins of the interface connector.

Memory sub-system manufacturing mode

Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

Efficient management of failed memory blocks in memory sub-systems

A determination is made by a processing device included in a memory component that an operation to program data to a location in the memory component has failed, the data is programmed to a different location in the memory component by the processing device upon determining the operation has failed, and a notification that the data has been programmed to the different location in the memory component is provided by the processing device to a processing device operatively coupled to the memory component.

Data redirection upon failure of a program operation

A power management system includes a memory component storing a plurality of configuration profiles. A plurality of configuration pins are operatively coupled to the memory component. One or more of the plurality of configuration pins receive one or more signals to selectively activate one of the plurality of configuration profiles.

Power configuration component including selectable configuration profiles corresponding to operating power characteristics of the power configuration component

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Meridian, ID, United States of America

Adam J Hieb