International Business Machines Corporation

Adam J Courchesne

Kenneth Joseph Goodnow

Serafino Bueti

Gregory John Mann

Jason Michael Norman

Stanley B Stanski

Scott T Vento

Peter Albert Twombly

Sebastian Theodore Ventrone

Kai D Feng

Peter Anthony Sandon

Todd Edwin Leonard

Charles S Woodruff

Francis A Kampf

Mark Steven Styduhar

Suzanne Granato

Kyle E Schneider

Jonathan P Ebbers

Eze Kamanu

Michael J Boudreaux

A method configures a plurality of circuit elements for execution of an application in a first configuration. The method monitors the execution of the application on the plurality of circuit elements to produce monitoring information, using a computerized device, and stores the monitoring information in a storage structure. The method selectively communicates the monitoring information to an external element separate from the computerized device. The external element transforms the first configuration into a second configuration based on the monitoring information. The computerized device receives the second configuration from the external element and reconfigures the plurality of elements into the second configuration.

Dynamically reconfigurable self-monitoring circuit

Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.

On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations

An adaptive lossless data compression method for compression of color image data in a data processing system. The method includes comparing a plurality of components of a plurality of adjacent pixels in a digital image, calculating spatial differences between the plurality of adjacent pixels, encoding the spatial differences and recording the encoded spatial differences, formatting an image file representing the digital image into byte streams based on bit significance, and compressing, independently, the byte streams associated with each bit significance of the encoded spatial differences.

Adaptive lossless data compression method for compression of color image data

A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

System and method for system-on-chip interconnect verification

An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner compatible with a customized, functional selection of individual ones of the IP cores, wherein individually selected cores are accessible through a communication structure included within the library.

Apparatus and method for implementing an integrated circuit IP core library architecture

An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.

Method and apparatus for monitoring integrated circuit temperature through deterministic path delays

A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to receive the communication signal from the power distribution network. A method is also provided for transmitting a communication signal via a power distribution network of a microelectronics chip.

Communication systems and methods using microelectronics power distribution network

A structure and associated method to control a flow of data on a semiconductor device. A transmitter, receiver and transmission line are formed within the semiconductor device. The transmitter, receiver, and transmission line are adapted to control data transfer between a first core and a second core within the semiconductor device. The transmitter is adapted to send a signal over the transmission line to the receiver adapted to receive the signal. The receiver is further adapted to create an impedance mismatch to indicate that the second core is unable to transfer the data. The transmitter is adapted to detect the impedance mismatch.

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Belchertown, MA, United States of America

Adam J Courchesne