Battelle Memorial Institute

Adam G Kimura

Daniel A Perkins

Andrew S Elliott

Rohan Prabhu

Noah Mun

Thomas Kent

Jeremy Bellay

Adam R Waite

Vince A McKinsey

In an integrated circuit (IC) analysis, a reference IC layout is stored. Instructions are readable and executable by an electronic processor to perform an IC analysis method, including: receiving layer images of a physical IC; extracting polygons depicted in the layer images; detecting errors in the physical IC by applying homeomorphic error detection to compare the extracted polygons with polygons of the reference IC layout; and displaying the detected errors on the display. The detecting of errors may include detecting an error comprising a topological inequivalence between an extracted polygon or pair of polygons and a polygon or pair of polygons of the reference IC layout. The detecting of errors may include detecting an error comprising a topological coverage error.

System and method for verification and validation of integrated circuit

A method of designing a robust integrated circuit that is not vulnerable to optical fault injection comprises training a variational autoencoder to identify regions in a target integrated circuit that are vulnerable to optical fault injection and altering the design of the target integrated circuit by altering the design of the vulnerable regions so that the target integrated circuit is no longer vulnerable to optical fault injection, thereby forming the robust integrated circuit.

Method of identifying vulnerable regions in an integrated circuit

In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.

Fabricated layout correlation

A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.

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Westerville, OH, United States of America

Adam G Kimura