Nxp B.v.

Nxp Usa, Inc.

Adam Fuks

Franciscus Petrus Widdershoven

Paul Kimelman

Ryan Haoyun Wu

Brian Christopher Kahne

Rob Cosaro

Satish Ravindran

Xiaomin Lu

Jurgen Holger Titus Geerlings

Philip Cupryk

Soong Boon Tong

Sergio Scaglia

Systems and methods for detection of persistent faults in processing units and memory have been described. In an illustrative, non-limiting embodiment, a Machine Learning (ML) processor includes one or more registers, and a data moving circuit coupled to the one or more registers. The data moving circuit can be configured to select, based upon a first value stored in the one or more registers, an original one of a plurality of parallel handling circuits within the ML processor to obtain an original data processing result. The data moving circuit can also be configured to select, based upon a second value stored in the one or more registers, an alternative one of the plurality of parallel handling circuits to obtain an alternative data processing result that, upon comparison with the original data processing result, provides an indication of a persistent fault in the ML processor.

Systems and methods for detection of persistent faults in processing units and memory

A scalable neural network accelerator may include a first circuit for selecting a sub array of an array of registers, wherein the sub array comprises LH rows of registers and LW columns of registers, and wherein LH and RH are integers. The accelerator may also include a register for storing a value that determines LH. In addition, the accelerator may include a first load circuit for loading data received from the memory bus into registers of the sub array.

Scalable neural network accelerator architecture

An early fusion network is provided that reduces network load and enables easier design of specialized ASIC edge processors through performing a portion of convolutional neural network layers at distributed edge and data-network processors prior to transmitting data to a centralized processor for fully-connected/deconvolutional neural networking processing. Embodiments can provide convolution and downsampling layer processing in association with the digital signal processors associated with edge sensors. Once the raw data is reduced to smaller feature maps through the convolution-downsampling process, this reduced data is transmitted to a central processor for further processing such as regression, classification, and segmentation, along with feature combination of the data from the sensors. In some embodiments, feature combination can be distributed to gateway or switch nodes closer to the edge sensors, thereby further reducing the data transferred to the central node and reducing the amount of computation performed there.

System and method for sensor fusion system having distributed convolutional neural network

Various exemplary embodiments relate to an event-driven processing unit (EPU) and a related method. A microprocessor may halt processing instructions when it executes a halting command. Thereafter, an EPU clock may stop its processing cycle and therefore halt microprocessor execution until it receives a start signal by a pattern detector. The pattern detector may use a plurality of bit slices to monitor a plurality of external inputs for the occurrence of events specified by the user. Some embodiments may also allow the user to check functioning by skipping upcoming instructions if a monitored event did not occur. By halting the EPU clock and the execution flow of the microprocessor, the event-driven microprocessor minimizes waste associated with executing a main control loop while waiting for a monitored event to occur. This may save processing capacity, memory, and power associated with continually running the main control loop.

Microprocessor to resume clocking and execution based on external input pattern detection

Embodiments of a method for operating an event-driven processor and an event-driven processor are described. In one embodiment, a method for operating an event-driven processor involves configuring a heartbeat timer of the event-driven processor and handling an event using the event-driven processor based on the heartbeat timer. Using a heartbeat timer built into the event-driven processor, the task execution determinism of the event-driven processor is improved and the power consumption of the event-driven processor is reduced. Other embodiments are also described.

Task execution determinism improvement for an event-driven processor

System and method for allocating memory resources are disclosed. The system utilizes a bus system coupled to a plurality of requestors and a plurality of memory systems coupled to the bus system. Each memory system includes a memory component and a memory management module including a value that represents access rights to the memory component. The memory management module is configured to receive an access request from a first requestor of the plurality of requestors and to grant access to the memory component only if the value indicates that the first requestor has access rights to the memory component. The memory management module is configurable to change the value to give the access rights to the memory component to a second requestor of the plurality of requestors.

System and method for allocating memory resources

A system and method for controlling an IC in different operational modes involves automatically loading operational configurations of target circuitries in the IC for a determined operational mode into at least one register and operating the target circuitries in the IC according to the operational configurations that are automatically loaded into the at least one register.

Growing community of inventors

Mountain View, CA, United States of America

Adam Fuks