Xilinx, Inc.

Adam Elkins

Wayne Edward Wennekamp

Schuyler E Shimanek

Thomas H Strader

Steven E McNeil

Roger D Flateau, Jr

John M Thendean

Mikhail A Wolf

Ephrem C Wu

James M Simkins

Amitava Majumdar

Richard Lewis Walke

Chidamber Kulkarni

Xiaoqian Zhang

Subodh Kumar

Uma E Durairajan

Joe E Leyba

Adnan Pratama

Yashodhara Parulkar

Ghazaleh Mirjafari

A digital signal processor (DSP) slice is disclosed. The DSP slice includes an input stage to receive a plurality of input signals, a pre-adder coupled to the input stage and configured to perform one or more operations on one or more of the plurality of input signals, and a multiplier coupled to the input stage and the pre-adder and configured to perform one or more multiplication operations on one or more of the plurality of input signals or the output of the pre-adder. The DSP slice further includes an arithmetic logic unit (ALU) coupled to the input stage, the pre-adder, and the multiplier. The ALU is configured to perform one or more mathematical or logical operations on one or more of the plurality of input signals, the output of the pre-adder, or the output of the multiplier. The DSP slice also includes an output stage coupled to the ALU, the output stage configured to generate one or more output signals based at least in part on one or more of the outputs of the ALU, or at least one of the plurality of input signals.

Digital signal processing block

Methods and apparatus are described for providing and operating an efficient infrastructure to implement a built-in clock stop and scan dump (CSSD) scheme for fabric blocks, such as block random access memory (BRAM), UltraRAM (URAM), digital signal processing (DSP) blocks, configurable logic elements (CLEs), and the like. This is a very useful feature for system debug and can also be applied for emulation use cases (e.g., FPGA emulation). This scheme can be applied to any tiled architecture that has highly repetitive blocks. The infrastructure may include a DFx controller shared across multiple tiled blocks with some distributed logic in each block, in an effort to minimize or at least reduce area overhead. The infrastructure may also minimize or at least reduce utilization of fabric resources in an effort to ensure the least perturbation of the original design, such that the design issues being debugged can be easily reproduced.

Efficient system debug infrastructure for tiled architecture

An apparatus is disclosed. This apparatus includes a digital signal processing ('DSP') block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit ('ALU') block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.

An embodiment of a technique to capture and locally synchronize data is disclosed. The technique includes receiving first and second signals through a first interface, and receiving a third signal through a second interface where the third signal is unsynchronized with respect to the second signal. The technique further includes detecting a first phase difference between the second and third signals, and generating a fourth signal in a manner so that a second phase difference between the fourth signal and one of the second or third signals is a function of the first phase difference. In addition, the technique includes storing a state of the first signal in response to the fourth signal, and thereafter supplying the stored state of the first signal to the second interface.

Method and apparatus for capturing and synchronizing data

A technique applicable during the transfer of data to and from a memory involves: operating a memory interface using memory access cycles that each transfer a quantity of data D across the memory interface; receiving a request to transfer a quantity of data Q across the memory interface; and calculating a value M as a function of a plurality of parameters, M being a minimum number of the memory access cycles needed to carry out the transfer of the quantity of data Q across the memory interface, wherein the calculating includes determining a logarithm of one of the parameters, and then determining the value M as a function of the logarithm.

Method and apparatus for calculating number of memory access cycles when transferring data to or from a memory

An embodiment of a technique to transfer data includes: operating a memory interface using memory access cycles that each include T successive time slots each provided for transfer of B bits of data, where T and B are positive integers; selecting one of first or second predetermined integers as one of T or B; and transferring a quantity of data Q between the memory interface and another interface. The transferring includes: automatically determining a value of M memory access cycles as a function of the one of T or B; causing a data transfer sequence on the memory interface that includes M successive memory access cycles and thus M&#xb7;T time slots; automatically determining a subset of the M&#xb7;T time slots as a function of the one of T or B; and transferring the quantity of data Q through the memory interface during the subset of time slots.

Method and apparatus for transferring data to or from a memory

An embodiment of a technique to transfer data between two different interfaces is disclosed. The embodiment of the technique includes: manipulating data arriving at a first data interface with a first word width into data with a second word width; transferring the manipulated data to a second data interface having the second word width; and selecting one of a plurality of different word widths for one of the first or second word widths.

Method and apparatus for transferring data between two different interfaces

A technique is provided for memory control in a device having programmable circuitry, including providing a dedicated memory controller circuit in the device before the programmable circuitry is field programmed. Another technique involves fabricating a device, where the fabricating involves forming programmable circuitry that includes a dedicated memory controller circuit before the circuitry is field programmed.

Method and apparatus for memory control with a programmable device

A device has first circuitry and also second circuitry that includes an interface and command ports that can each receive commands from the first circuitry, each command requesting an information transfer through the interface. A technique relating to the device involves dynamically enabling and disabling at least one of the command ports under control of the first circuitry, and using a priority list specifying an order of priority for a group of the command ports to identify and cause a command to be accepted from the command port of highest priority that contains a command and is currently enabled.

Method and apparatus for arbitration among multiple ports

An apparatus includes a programmable device that has an interface and command ports that can each receive commands, each command requesting an information transfer through the interface. A technique relating to the device involves: selecting during field programming a number of priority definitions; configuring each of the priority definitions during field programming to specify an order of priority for a group of the command ports; and using the priority definitions in succession and, for each of the priority definitions, causing a command to be accepted from the command port of highest priority that contains a command.

Method and apparatus for multi-port arbitration using multiple time slots

Within an integrated circuit comprising a memory controller, a method can include, responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting of the delay circuit. The new maximum value specifies a number of taps of the delay circuit that approximates a predetermined time span. The method can include dynamically adjusting a delay applied to a signal by a delay circuit according to the new tap setting. The delay circuit generates a delayed signal that is provided to the memory controller.

Dynamic signal calibration for a high speed memory controller

A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled between the first and second interfaces. The technique includes configuring the interconnect structure during field programming to electrically couple each of the address terminals in a first subset of the first address terminals to respective address terminals in a second subset of the second address terminals according to a selected one of a plurality of different mapping functions.

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Rio Rancho, NM, United States of America

Adam Elkins