Nvidia Corporation

Easic Corporation

Silicon Gaming, Inc.

Silicon Gaming-nevada

Adam E Levinthal

Allan E Alcorn

Michael Barnett

Louis D Giacalone, Jr

Zvi Or-Bach

Jonah Matthew Alben

Sean Jeffrey Treichler

Ze'ev Wurman

Wayne Douglas Young

Brijesh Tripathi

Adrian Apostol

Richard Zeman

Romeo Iacobut

Petrica Avram

Stephen M Ryan

Herman Henry Schmit

Laurence Hager Cooke

Philip Browning Johnson

Jonathan C Park

George Grigore

Ronnie V Vasishta

Stan Mihelcic

Alon Kapel

Ze′ev Wurman

Louis D Giacalone

Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.

Memory clock slowdown

A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.

Programmable vias for structured ASICs

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.

Structured integrated circuit device

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.

A graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a buffer including a buffering space shared by the memory clients. The buffering module also includes a buffer controller connected to the buffer. The buffer controller is configured to: (1) dynamically assign portions of the buffering space to respective ones of the memory clients; (2) coordinate storage of the data in the assigned portions; and (3) coordinate delivery of the data from the assigned portions to respective ones of the memory clients.

Apparatus, system, and method for delivering data to multiple memory clients via a unitary buffer

Apparatus, system, and method for delivering data to multiple memory clients are described. In one embodiment, a graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the set of memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a unitary buffer and a buffer controller connected to the unitary buffer. The buffer controller is configured to coordinate storage of the data in the unitary buffer, and the buffer controller is configured to coordinate delivery of the data from the unitary buffer to respective ones of the set of memory clients.

The electronic casino gaming system consists of several system components, including a microprocessor (), a main memory unit () that is typically a random access memory, and a system boot ROM (). Also included in the electronic casino gaming system are a non-volatile RAM (), a mass storage unit (), a disk subsystem (), and a PCI bus (). The disk subsystem () preferably supports SCSI-2 with options of fast and wide. A video subsystem () is also included in the electronic casino gaming system and is coupled to the PCI bus () to provide full color still images and MPEG movies.

Electronic casino gaming system with improved play capacity, authentication and security

The electronic casino gaming system consists of several system components, including a microprocessor (), a main memory unit () that is typically a random access memory, and a system boot ROM (). Also included in the electronic casino gaming system are a non-volatile RAM (), a mass storage unit (), a disk subsystem (), and a PCI bus (). The disk subsystem () preferably supports SCSI-with options of fast and wide. A video subsystem () is also included in the electronic casino gaming system and is coupled to the PCI bus () to provide full color still images and MPEG movies.

Growing community of inventors

Redwood City, CA, United States of America

Adam E Levinthal