USA As Represented by Secretary of the Navy

Other

Adam Duncan

Matthew Gadlage

Matthew J Kay

James David Ingalls

Austin H Roach

Andrew Mark Howard

Brett J Hamilton

Patrick L Cole

Jeffrey L Titus

Matthew John Gadladge

Glenn Berger

Brett Werner

Mark Savage

Andrew Lukefahr

Douglas J Martin

Fred Barsun

A field-programmable gate array (FPGA) architecture capable of performing immutable hardware Root-of-Trust updates and patches. In embodiments, the architecture utilizes the dielectric breakdown mechanism of magneto tunnel junctions (MTJ) to operate both as: 1) multi-time programmable (MTP) configuration memory for reconfigurable FPGA designs, and 2) one-time programmable (OTP) memory for FPGA Root-of-Trust sections.

Field-programmable gate array with updatable security schemes

Various embodiments include providing a MTJ-based LUT and adding a system that short circuits or causes dielectric layer breakdown of selected MTJ junctions to permanently finalize a desired logic state configuration of selected MTJs that is read out by the LUT. Additional embodiments disable dielectric layer breakdown or short circuit control circuits to prevent further alterations to MTJ that have not had their dielectric layers broken down or shorted out. A control system then alters reading out the MTJ-based LUT to sense original higher and lower resistance values of un-shorted/altered MTJs as a higher resistance state and a shorted or dielectric layer that has been broken down as a lower resistance state. This combines the flexibility of a multiple-time programmable LUT-based FPGA with the security and reliability of a one-time programmable LUT-based FPGA which has characteristics of a fixed logic non-programmable integrated circuit or application specific integrated circuit (ASIC).

Non-volatile multiple time programmable integrated circuit system with selective conversion to one time programmable or permanent configuration bit programming capabilities and related methods

Apparatuses and methods using current-starved ring oscillator biased by floating gate transistors with a variety of applications including as a power-free radiation detector or silicon age determination or odometer system.

Apparatuses and methods using current-starved ring oscillator biased by floating gate transistors with a variety of applications including as a power-free radiation detector or silicon age determination or odometer system

Various apparatus and methods associated with a compact electronics test system having user programmable device interfaces and on-board functions adapted for use in various environments are provided. Exemplary embodiments can include a variety of apparatuses and methods to realize an advanced field programmable gate array adapted to perform functional tests on digital electronics within an exemplary 48-pin DIP footprint. One aspect of the invention can include a testing device comprised of components to produce a product that is inexpensive and consumable. A small size of an exemplary embodiment of the invention further allows for desirable shielding to be placed around a highly portable and highly programmable and adaptable testing device in order to protect it from external dangers found in harsh environments (e.g., high levels of radiation when operating in space, etc.).

Compact electronics test system having user programmable device interfaces and on-board functions adapted for use in proximity to a radiation field

Exemplary systems and methods for inhibiting backend access to an integrated circuit are provided including latch-up circuits triggered by photons, electrons, and ions to create catastrophic failures in integrated circuits. Exemplary systems include latch-up circuits with floating gate bit cells which, when triggered, close the latch-up circuits so that the latch-up circuits can amplify current in a positive feedback loop to create a short circuit to inhibit unauthorized individuals from probing or modifying an integrated circuit.

Systems and methods for inhibiting backend access to integrated circuits by integrating photon and electron sensing latch-up circuits

A highly flexible, compact, lightweight, and portable testing system for use with radiation testing activities. The testing system is coupled to a device under test (DUT), which can be positioned in such a way that the top of the die package is exposed to the direct ion beam during radiation testing. A variety of sensors, onboard memory systems, programmable interfaces, onboard control systems, data output devices, and different types of interfaces are also provided which provide an ability to perform testing procedures while having a maximum ability to orient the DUT and perform a wide variety of testing currently unavailable.

Digital test system

A method and system for determining short, open, and good connections using digital input and output (TO) structures in a device under test (DUT) continuity test, through the combined methods of using resistance-capacitance (RC) delay, time domain reflectometry (TDR), and forcing voltage on to a single IO pin of the DUT while measuring voltage on remaining IO pins of said DUT. In one embodiment, the combined methods are executed without the DUT in a test socket to produce a first set of test values and also with the DUT in a test socket to produce a second set of test values. The first and second sets of test values are compared to determine if one or more circuits of the DUT have a short circuit, an open circuit, or are a good (have an electrical connection that is not a short circuit or an open circuit) circuit.

DUT continuity test with only digital IO structures apparatus and methods associated thereof

A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.

Method and system for improving the radiation tolerance of floating gate memories

A method and system for determining short, open, and good connections using digital input and output (IO) structures in a device under test (DUT) continuity test, through the combined methods of using resistance-capacitance (RC) delay, time domain reflectometry (TDR), and forcing voltage on to a single IO pin of the DUT while measuring voltage on remaining IO pins of said DUT. In one embodiment, the combined methods are executed without the DUT in a test socket to produce a first set of test values and also with the DUT in a test socket to produce a second set of test values. The first and second sets of test values are compared to determine if one or more circuits of the DUT have a short circuit, an open circuit, or are a good (have an electrical connection that is not a short circuit or an open circuit) circuit.

An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus is provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.

Irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus

Apparatuses and methods are provided using a plurality of interrupted IC operations to detect various conditions or changes of interest to integrated circuit (IC) elements (e.g., memory cells of NAND Flash memories or floating gate transistor) such as program/erase stress, total ionizing dose, and heavy ion exposure which modify normal IC element bit state changes. An exemplary method can include controlling a plurality of selected IC elements to execute a series of PROGRAM or ERASE operations on all of the plurality of selected elements that are each interrupted or halted before a normal or first time period required for the PROGRAM or ERASE operation has elapsed. An exemplary system records a number of interrupted operations required to cause a state change in each of the plurality of selected IC elements. Embodiments of the invention enable detection of stresses far below at least some thresholds for IC element or bit cell failure.

Methods and apparatuses including one or more interrupted integrated circuit operations for characterizing radiation effects in integrated circuits

An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus are provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.

Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using a combination of a metal-oxide semiconductor field effect transistor (MOSFET) and junction field effect transistor (JFET) disposed perpendicularly and within a certain orientation to each other. An embodiment of the invention can be formed and operable for modulating current and/or voltage response or mitigating electromagnetic or radiation interference effects on the MOSFET by controlling a semi-conductive channel region (SCR) using an additional gate, e.g., JFET, disposed perpendicularly with respect to the MOSFET configured to generate an electromagnetic field into the MOSFET's semi-SCR. A control system for controlling operation is also provided to include automated systems including sensors as well as manually operated systems. Automated systems can include radiation sensors as well as other control systems such as radio frequency transmitter or receiver systems. Methods of operation for a variety of modes are also provided.

Combination metal oxide semi-conductor field effect transistor (MOSFET) and junction field effect transistor (JFET) operable for modulating current voltage response or mitigating electromagnetic or radiation interference effects by altering current flow through the MOSFETs semi-conductive channel region (SCR)

Various apparatus and method s associated with a compact electronics test system having user programmable device interfaces and on-board functions adapted for use in various environments are provided. Exemplary embodiments can include a variety of apparatuses and method s to realize an advanced field programmable gate array adapted to perform functional tests on digital electronics within an exemplary 48-pin DIP footprint. One aspect of the invention can include a testing device comprised of components to produce a product that is inexpensive and consumable. A small size of an exemplary embodiment of the invention further allows for desirable shielding to be placed around a highly portable and highly programmable and adaptable testing device in order to protect it from external dangers found in harsh environments (e.g., high levels of radiation when operating in space, etc).

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Bloomington, IN, United States of America

Adam Duncan