Synopsys, Inc.

Adam Cron

Michael Andrew Borza

Andrew Alexander Elias

Bandi Chandra Sekhar Reddy

A method of obfuscating a circuit design includes, in part, receiving data representative of the circuit design. The method further includes, in part, simulating the circuit design, and obfuscating at least one output signal of the circuit design if a user performing the simulation is determined as not being an authorized user.

Obfuscating encrypted register transfer logic model of a circuit

Some aspects of this disclosure are directed to implementing hardware-based obfuscation of digital data. For example, some aspects of this disclosure relate to a method, including performing a capture operation that loads a plurality of primary input (PI) bits into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits. The method further includes performing a sequence of shift operations on the plurality of TDRs to obtain a plurality of output bits. The method further includes applying, by an authenticating processor, a derivation function on the plurality of output bits to extract the plurality of secret information bits thereby authenticating the one or more digital semiconductor devices.

Hardware-based obfuscation of digital data

A save and restore (SR) register system is disclosed. Some embodiments include a first memory state element (MSE), a second MSE, and a control circuit. The first MSE is configured to: clock in a first data value during a normal mode and hold the first data value during a first testing mode; and clock in a first test sequence during a second testing mode. The second MSE is configured to: clock in the first data value during the normal mode; and clock in a second test sequence during the first testing mode. The control circuit configured to: restore the second MSE to the first data value based on an output port of the first MSE after the second MSE clocks in the second test sequence; and restore the first MSE based on an output port of the second MSE after the first MSE clocks in the first test sequence.

Save and restore register

An augmented simulation model can be created of an integrated circuit (IC) design by inserting a switch in a simulation model of the IC design between an output of a scan cell and an input of a combinational logic cloud. A simulation enable signal can be used to control the switch. Next, an IC design simulation environment can be generated based on the augmented simulation model. The IC design can be verified by using the IC design simulation environment. The simulation enable signal can be activated when the combinational logic cloud is desired to be simulated by the IC design simulation environment.

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Hilton Head Island, SC, United States of America

Adam Cron