Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Agere Systems Inc.

Avago Technologies International Sales Pte. Limited

Adam Benjamin Healey

Chaitanya Palusa

Pervez Mirza Aziz

Volodymyr Shvydun

Hiep The Pham

Tomasz Prokop

Amaresh Virupanagouda Malipatil

Magesh Valliappan

Mohammad Shafiul Mobin

Mark A Bordogna

Ye Liu

Shawn Michael Logan

Lane Allen Smith

Viswanath Annampedu

Gregory W Sheets

Lizhi Zhong

Paul H Tracy

Mark J Marlett

Geoffrey Zhang

Stephen S Oh

Sunil Srinivasa

Gary Schiessler

Sundararajan Cidambara

Peter A Stropparo

A digital signal processing (DSP)-based serializer-deserializer (SERDES) includes a first filter configured to mitigate inter-symbol interference (ISI) attributed to dispersion associated with a long-reach transmission medium. The SERDES includes a second filter configured to shape the ISI. The SERDES includes also includes a third filter coupled in parallel with the second filter and configured to reduce ISI attributed to reflections associated to both near-zero delays and long delays.

Efficient architecture for high-performance DSP-based long-reach SERDES

A digital signal processing (DSP) device includes a first fitter to equalize channel dispersion associated with signal transmission through a medium, a second filter to cancel channel reflections, and a third filter to at least reduce noise. The DSP device is a receiver DSP of the SERDES.

Efficient architecture for high-performance DSP-based SERDES

The present disclosure is directed to systems, apparatuses, and methods for performing continuous or periodic link training. Existing link training protocols generally perform link training only once during startup or initialization of a link and, as a result, are limited in their applications. After link training is performed and Open Systems Interconnect (OSI) data link layer and other high-layer data is transmitted across the link, no further link training is performed using these existing link training protocols. However, parameters of the link may change over time after link training is performed, such as temperature of the link and voltage levels of signals transmitted over the link by the transmitter of the transmitter-receiver pair.

High-speed interconnect solutions with support for secondary continuous time in-band back channel communication for simplex retimer solutions

High-speed interconnect solutions with support for co-propagating and counter-propagating continuous time back channel communication

High-speed interconnect solutions with support for continuous time back channel communication

High-speed interconnect solutions with support for continuous time in-band back channel communication and proprietary features

Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.

Modular low power serializer-deserializer

Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.

Baud rate phase detector with no error latches

A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.

Method and apparatus for pre-cursor intersymbol interference correction

An interleaved track-and-hold front-end with multiphase clocks computes and propagates unrolled decision feedback equalization results along a pipeline with the final outputs selected from one of the interleaved previous output bits with a multiplexer operating over multiple unit intervals instead of one unit interval. An n-way interleaved serializer/deserializer utilizes an n unit interval multiplexer or n one unit interval multiplexers. Pipelined decision feedback equalization allows multiple, slower multiplexers.

Pipelined decision feedback equalization in an interleaved serializer/deserializer receiver

A SerDes receiver device can receive binary signals via wireline channel such that information recovery is primarily or entirely performed via DSP algorithms in the digital domain includes an analog to digital converter, adaptation and calibration blocks, and a sequential n-way parallel equalization data path. The data path provides preliminary equalization of digital input symbols through a feed forward equalizer block followed by a decision feedback equalizer block, to which a k-slice decision feed forward equalizer block is appended for generating equalized hard decision outputs. The decision feed forward equalizer block may include a concatenation of cascading DFFE slices to improve the performance of the data path.

DSP SerDes receiver with FFE-DFE-DFFE data path

A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.

Code forwarding and clock generation for transmitter repeaters

A reconfigurable P-way parallel N-tap feed forward equalizer includes an adaptive filter configured to generate a series of coefficients (taps) and an input register for storing input symbols. A variable cursor position defined by a parameter corresponding to a position in the input register selects a set of pre-cursor and post-cursor taps for dynamic ISI correction of a like set of pre-cursor and post-cursor symbols. Multiplier banks generate partial result symbols by applying the taps to the set of input symbols, and a set of combiners or adder banks generate equalized output symbols from the partial result symbols. Two multiplexers adjust input symbols and coefficients according to the parameter, and a controller allows selection of an optimal parameter, and thus an optimal variable cursor position. The coefficient corresponding to the parameter may additionally be preset to save storage space.

Method and apparatus for feed forward equalizer with variable cursor position

The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver based on the normalized Nyquist energy.

System and method for determining channel loss in a dispersive communication channel at the Nyquist frequency

An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.

Growing community of inventors

Newburyport, MA, United States of America

Adam Benjamin Healey