International Business Machines Corporation

Cypress Semiconductor Corporation

Infineon Technologies North America Corp.

Adam B Wilson

Russell J Houghton

Thomas Vogelsang

Ryan A Jurasek

William R Tonti

John Atkinson Fifield

Richard Michael Parent

Duane E Galbi

Michael A Killian

A method and apparatus for power supply rejection in a reference voltage circuit using a variable resistance circuit.

Reference voltage circuit

A voltage trim circuit, in accordance with one embodiment of the invention, includes an operational amplifier, a transistor, a voltage divider and a bias current circuit. The operational amplifier is coupled to an input. The transistor is coupled to the operational amplifier and a first potential. The voltage divider circuit is coupled to the operational amplifier, the transistor and an output. The bias current circuit is coupled to the voltage divider circuit and a second potential. The voltage divider generates an output voltage as a function of a selectable divider ratio and provides a substantially constant feedback path to the operational amplifier. The bias current circuit provides for selectively adjusting a load resistance of the transistor to maintain a substantially constant load current through the transistor.

Method and circuit for adjusting a reference voltage signal

A logic circuit implementing a logic function and method of manufacture thereof. The logic circuit includes a series connection of two or more CMOS devices, at least one CMOS device having a threshold voltage at an input lower than a threshold voltage at an input of another of the CMOS devices. The CMOS logic circuit exhibits enhanced switching speed for logic operations and reduced leakage current when operating in an off-state. A logic family is built around the series connection of two or more devices having mixed voltage threshold inputs for enhanced switching speed and reduced off-current leakage.

Mixed threshold voltage CMOS logic device and method of manufacture therefor

An off-chip driver circuit with compensated current source including a reference current amplifier and an output driver with a pull-up section. The reference current amplifier includes an input voltage Vcmn from an on chip current reference source. A reference current is established in the reference current amplifier by choosing the Beta of transistor in a current path. A feature of the circuit is that an output current is produced in the output lead of the driver circuit that is proportional to the current in the reference current amplifier, but with adjustments made for the supply voltage level and effective transistor channel length, Leff. Another feature of the circuit is that a reference current-voltage is established on the output lead of the reference current amplifier that is primarily determined by a multiple of the reference current but is reduced by a function of the supply voltage. In the circuit the output current of the driver is reduced linearly and predictably with the supply voltage.

Compensated-current mirror off-chip driver

A method of testing a semiconductor circuit, the semiconductor circuit including word lines connected to a storage device, address receivers receiving addresses, an address decoder decoding the addresses and selecting ones of the word lines, a self-refresh unit refreshing the word lines during a non-test mode and a test mode device controlling the semiconductor circuit in a test mode, the method comprises supplying a test mode signal to the test mode device, activating a test mode operation of the self-refresh unit, sequentially activating the word lines using the self-refresh unit, maintaining the word lines in an active condition for a predetermined time period and deactivating the word lines.

Timing of wordline activation for DC burn-in of a DRAM with the

A voltage regulator for DRAM chips having known short duration high current load events started by a trigger signal includes a regulating transistor operating in the weak inversion mode and a boost driver circuit. The trigger signal that starts the load event also triggers the boost driver circuit to produce a shaped boost signal at the correct time. The boost signal is applied to the gate of the regulating transistor to counteract the expected voltage drop at the output of the regulating transistor. The expected voltage drop is due to the known characteristics of the regulating transistor which include a change in threshold voltage of the regulating transistor during the high current flow of the load event. A switch device disconnects a preregulator during the load event and reconnects the preregulator thereafter. The boost signal is preferably applied to the regulating transistor through a capacitive divider.

Weak inversion NMOS regulator with boosted gate

An off-chip driver with regulated supplies compensates for power supply fluctuations. The circuit reduces di/dt noise by providing complementary voltage regulators to regulate the high and low supplies to the driver stages such that they see a constant operating voltage regardless of changes in supply voltage, V.sub.CC. The circuit uses two push-pull stages which charge and discharge the output load capacitance, C.sub.0. This regulated voltage to the driver stages reduces di/dt noise and provides a constant overdrive voltage, constant gate slew rate, and constant staging delay over a specified external supply voltage range.

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Colchester, VT, United States of America

Adam B Wilson