Silicon Laboratories Inc.

University of California

Adam B Eldredge

Susumu Hara

Yunteng Huang

Xue-Mei Gong

Zhuo Fu

Jeffrey S Batchelor

Gary Hammes

Peter A Krulevitch

Frederick F Becker

Julie K Hamilton

Bernhard Boser

Xiao-Bo Wang

Gregory Jon Richmond

Peter R C Gascoyne

Harold D Ackler

Stefan P Swierkowski

Christopher K Fuller

James E Wilson

Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.

Fail safe clock buffer and clock generator

A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function.

Higher-order phase noise modulator to reduce spurs and quantization noise

A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal.

Interpolative divider linearity enhancement techniques

An apparatus includes a first conductive loop coupled to conduct a first current and a second conductive loop coupled in parallel with the first conductive loop and further coupled to conduct a second current. A first conductive portion forms a part of the first conductive loop and the second conductive loop. The first conductive portion is coupled to conduct the first current and the second current. In at least one embodiment of the apparatus, the first conductive loop and the second conductive loop are planar inductors formed in a conductive layer on a substrate of an integrated circuit.

Mutual inductance circuits

A method includes operating on a sigma-delta modulated signal to reduce a dither signal component in one of a first signal and a second signal, the first signal being an integer portion corresponding to a digital frequency ratio and the second signal corresponding to a fractional portion of the digital frequency ratio. In at least one embodiment of the method, the operation is performed digitally in a frequency synthesizer.

Sigma-delta modulation with reduction of spurs using a dither signal

One or more PLLs are formed on an integrated circuit. Each PLL includes an interpolative divider configured as a digitally controlled oscillator, which receives a reference clock signal and supplies an output signal divided according to a divide ratio. A feedback divider is coupled to the output signal of the interpolative divider and supplies a divided output signal as a feedback signal. A phase detector receives the feedback signal and a clock signal to which the PLL locks. The phase detector supplies a phase error corresponding to a difference between the clock signal and the feedback signal and the divide ratio is adjusted according to the phase error.

PLL using interpolative divider as digitally controlled oscillator

The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed.

Calibrating a phase detector and analog-to-digital converter offset and gain

In one embodiment, the present invention includes a system having an amplifier to receive an incoming signal and a recovery circuit coupled to the amplifier that includes a phase detector to adjust a phase of a sampling clock via a signal indicative of a difference between transitions occurring between the sampling clock and each of a first error clock and a second error clock. Based on a phase adjusted output of the phase detector, the sampling clock may be generated with an appropriate phase. Thus, circuitry and methods are provided to reduce or eliminate phase offsets in the phase detector.

Reducing phase offsets in a phase detector

Embodiments of the present invention may provide for independent setting of jitter tolerance and jitter transfer levels, and reduced jitter generation of a data transmission device, such as a clock and data recovery (CDR) circuit or the like. An architecture may provide for reconfigurability of a circuit for use in various applications. The architecture may include a multi-loop structure, such as a tri-loop structure.

Data cleaning with an asynchronous reference clock

An output of an oscillator of a phase-locked loop is swept across a predetermined frequency range by varying control settings associated with the oscillator. A plurality of control settings that cause the oscillator to lock or falsely lock to the timing of an input data stream are determined at least in part according to a bit error rate. The bit error rate is based on transitions of the input data stream occurring in an error zone, the error zone being a predefined phase zone of a sample clock sampling the input data stream. When two control settings that cause the oscillator to lock or false lock are in a same locking region based on proximity of the control settings to each other, a preferred control setting is determined between the two according to respective values of the two control settings. True lock settings are distinguished from false lock settings based on an evaluation of bit errors that occur in an expanded error zone.

Robust false locking prevention in referenceless frequency acquisition

In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a wide range of levels extending from a low end lower than a supply voltage of the input buffer to a high end exceeding the supply voltage.

Input buffer

In one embodiment, a method may determine a number of data transitions occurring in a forbidden zone at each of a first and second slice levels and adjust a slice level offset for an amplifier based on the number of data transitions at the first and second slice levels. Furthermore, a phase window of the forbidden zone may be adjusted to attain a desired bit error rate for a receiver.

Determining signal quality and selecting a slice level via a forbidden zone

A microfabricated instrument for detecting and identifying cells and other particles based on alternating current (AC) impedance measurements. The microfabricated AC impedance sensor includes two critical elements: 1) a microfluidic chip, preferably of glass substrates, having at least one microchannel therein and with electrodes patterned on both substrates, and 2) electrical circuits that connect to the electrodes on the microfluidic chip and detect signals associated with particles traveling down the microchannels. These circuits enable multiple AC impedance measurements of individual particles at high throughput rates with sufficient resolution to identify different particle and cell types as appropriate for environmental detection and clinical diagnostic applications.

Growing community of inventors

Austin, TX, United States of America

Adam B Eldredge