International Business Machines Corporation

Adalberto Guillermo Yanes

Timothy J Fisher

Steven Mark Thurber

Daniel Frank Moertl

Danny Marvin Neal

Aaron Daniel Fry

Curtis Carl Wollbrink

Lincoln T Simmons

Charles John Camp

William Joseph Armstrong

Gregory Michael Nordstrom

David R Engebretsen

Kevin E Sallese

Nikolaos Papandreou

Brent Cameron Beardsley

Richard Allen Kelley

Patrick Allen Buckland

Scott Neil Dunham

Jason Szecheong Ma

Charles A Keller

Van Huynh

Sudha Sarma

Charles Scott Graham

Eric N Lais

Carl Alfred Bender

Pat Allen Buckland

David C Giese

Cyril Varkey

Michael T Benhase

Roman Alexander Pletka

Charalampos Pozidis

Andrew Dale Walls

Nikolas Ioannou

Enrique Q Garcia

Radu Ioan Stoica

Scott Michael Willenborg

Michael Anthony Perez

Steven Paul Jones

Damon W Finney

James C Chen

Juan Antonio Yanes

Ryan Scott Haraden

Donald J Lang

Kiet Anh Tran

Forrest Lee Wade

Mark C Johnson

Jonathan Michael Allen

George B Marenin

Lawrence Dean Whitley

William G Sherman, Ii

Michael Curtis

James Richard Pollock

Matthew S Reuter

Thomas K Pokrandt

Lawrence Marcel Brown

Kevin Dale Jones

Michael S Porter

Kevin G Zitny

Donald J Albin

A computer-implemented method, according to one embodiment, is for performing garbage collection. The computer-implemented method includes: causing pages in non-volatile memory that are due for garbage collection to be inspected, and causing certain ones of the pages in the non-volatile memory having valid data therein to be identified. Each of the pages of non-volatile memory includes multiple planes, and the valid data is included in one or more of the planes in the respective identified pages. Recirculation requests, that selectively exclude planes in the identified pages that do not include any of the valid data, are further sent to a recirculation pool.

Increased garbage collection granularity for non-volatile memory

Provided are a memory controller, system, and method for generating multi-plane reads to read pages on planes of a storage die for a page to read. A memory controller determines planes for a read to a page. A storage die of the storage dies includes a plurality of planes having a plurality of blocks and the blocks have pages. The page to read is implemented in pages on the planes. The memory controller determines threshold voltages for the pages in the determined planes and determines a derived threshold voltage from the determined threshold voltages. The derived threshold voltage is used to perform multi-plane reads of the pages from the determined planes.

Generating multi-plane reads to read pages on planes of a storage die for a page to read

A computer-implemented method, according to one embodiment, includes: receiving, in first and second read request buffers corresponding to first and second computer interface links of a data storage system, read requests. Read completion data corresponding to the read requests being performed is also received. The read completion data is allocated between first and second read completion buffers based on which of the read completion buffers has a greater amount of available space therein. Furthermore, the read completion data in the first and second read completion buffers is sent. The first read completion buffer corresponds to the first computer interface link and the second read completion buffer corresponds to the second computer interface link.

Increased read performance for implementations having multiple interface links

A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.

Mirroring data in write caches of a controller of a non-volatile memory

A computer-implemented method, according to one embodiment, includes: receiving a stream of data, and selecting more than one block of memory to write the stream of data to. The selected blocks of memory are in a memory that includes a plurality of blocks. Moreover, the data is written across the selected blocks of memory in parallel. The blocks of memory are also selected such that no two or more of the selected blocks of memory have an effect on a read apparent voltage of a same one of the plurality of blocks in the memory. Other systems, methods, and computer program products are described in additional embodiments.

Reducing effects of read array operations of read apparent voltage

Read Apparent Voltage (RAV) is an anomality in which an apparent threshold voltage of a storage cell transistor does not equal the actual threshold voltage of that same transistor by a large enough magnitude that the binary state of transistor is not read correctly. An infector page may cause the RAV anomality within a different infected page. To determine whether any page is an infector, each page is programmed, a page within each block is read, an acting infector page within an acting infector block is set, a possible infected page within a possible infected block is set, the acting infector page is read a predetermined plurality of instances, the possible infected page is read, a raw bit error rate (RBER) of the read of the possible infected page is determined, and the acting infector page is set as an actual infector page based upon the determined RBER.

Determining a read apparent voltage infector page and infected page

A data storage system includes a non-volatile memory array controlled by a controller that records a number of a plurality of like operations targeting a first block among a plurality of blocks in the non-volatile memory array. In response to the number of the plurality of like operations satisfying a threshold, the controller initiates a mitigation read request by recording an identifier of a second block in a high priority request in a mitigation data structure. The controller initiates other mitigation read requests by recording identifiers of other blocks of the non-volatile memory in low priority requests in the mitigation data structure. The controller preferentially services the high priority request from the mitigation data structure over the low priority requests, where servicing the high priority request includes performing a mitigation read to the second block.

Reducing read errors by performing mitigation reads to blocks of non-volatile memory

Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.

Peripheral component interconnect express (PCIE) pseudo-virtual channels using vendor defined messages

A method, according to one embodiment, includes: receiving a recirculation command; performing a coarse page lookup to determine valid ones of logical pages to be recirculated; requesting performance of a fine page lookup on source physical addresses containing the valid logical pages to verify the valid logical pages; and sending write commands corresponding to verified valid logical pages from the fine page lookup. Other systems, methods, and computer program products are described in additional embodiments.

Accelerated non-volatile memory recirculation processing

A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Validation bits and offsets to represent logical pages split between data containers

A method, according to one embodiment, includes: receiving a recirculation command, performing a coarse page lookup to determine valid ones of logical pages to be recirculated, issuing write commands for the valid logical pages, requesting performance of a fine page lookup on source physical addresses containing the valid logical pages to verify the valid logical pages, receiving verified valid logical pages resulting from the fine page lookup, and sending the write commands corresponding to the verified valid logical pages. Other systems, methods, and computer program products are described in additional embodiments.

Flash memory codeword architectures

Growing community of inventors

Rochester, MN, United States of America

Adalberto Guillermo Yanes