Intel Corporation

Apple Inc.

Hewlett-Packard Development Company, L.p.

Idea Corporation

Institute for the Development of Emerging Architectures, L.l.c.

Idea Corporation of Delaware

Achmed Rumi Zahir

Jonathan Kent Ross

Inder M Sodhi

Carol Linda Thompson

Cary Allen Coutant

Keith Alan Cox

Thomas E Willis

James S Ismail

Lior Zimet

Liran Fishel

Omri Flint

Ami Schwartzman

Satish B Acharya

Dale Calvin Morris

Tse-Yu Yeh

John Meron Ananny

Ralph Michael Kling

Arvind Mandhani

Bruce L Fleming

Jan Krellner

Vincent E Hummel

Ron Neuman

Reza Arastoo

Daniele Perretta

Carmel Yamberger

Gilbert A Neiger

Varghese George

Sanjeev S Jahagirdar

Richard A Uhlig

Doron Rajwan

Koichi Yamada

Ioannis T Schoinas

Gary N Hammond

John H Crawford

Prashant H Vashi

Dean A Mulla

Michael T Klinglesmith

John Gregory Dorsey

Rajesh Sankaran Madukkarumukumana

Douglas Raymond Moran

Bryan R Hinch

Tal Kuzi

Michael Eng

Vasudev Bibikar

John H Kelm

Aditya Venkataraman

Allan Douglas Knies

Prasad A Raje

Daniel U Becker

William Knolla

Amy L O'Donnell

Michael Victor Yeh

Sunil Saxena

Irwin J Vaz

Ku-jei King

Hao Ping Wen

Jeffrey Baxter

Hartej Singh

Karl Daniel Wulcan

Punit H Awatramani

Murali Mohan Chakka

Douglas A Mackay

Mingkun Li

Cary Coutant

Sean G Galloway

Donald C Soltis

Luca Aldegheri

Priyank Mamania

Vasanthakumar Balasubramaniam

De Jun Li

Amir Rajaee

Tu Le

Diwakar N Tundlam

Douglas A MacKay

Jonathon K Ross

Carol Thompson

Techniques are disclosed relating to electromigration control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor operating conditions, implement control for one or more electromigration loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid electromigration issues, potentially with reduced impact on processor performance relative to traditional techniques.

PMU-side electromigration control

Communication device may include a transmitter and a receiver respectively coupled to one or more antennas to communicate (e.g., transmit or receive signals) with a base station. The communication device may receive an operating characteristic of a cellular modem within the communication device operating in a first cellular configuration and determine if the operating characteristic are greater than a threshold. The operating characteristic may include power and/or temperature. The threshold may include a power budget and/or a temperature threshold. If the operating characteristic is greater than the threshold, then the communication device may determine a control effort value based on the operating characteristic and the threshold. The communication device may map the control effort value to a second cellular configuration, which may correspond to reduced operating characteristics in comparison to the first cellular configuration. The communication device may then cause the cellular modem to operate in the second cellular configuration.

PI controller for cellular baseband mitigation

Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

Blocking latency events in multi-die architecture

Techniques are disclosed relating to thermal control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor thermal conditions, implement control for one or more thermal loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid thermal issues, potentially with reduced impact on processor performance relative to traditional techniques.

PMU-side thermal control

Synchronizing power state changes between multiple dies

Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Specifically, a power manager circuit in an integrated circuit (e.g., a system on a chip) may modify power budgets for various components in the integrated circuit to reduce the amount of power control caused by external signaling that indicates a voltage regulator overload (e.g., a voltage droop).

Power management based on limiting hardware-forced power control

Systems and methods are disclosed for allocating and distributing power management budgets for subsystems (e.g., power usage clients) of a computer system. A power budget allocation subsystem may include a plurality of feedback branches having different associated time constants. Power usage clients with slower power response times may be provided power budgets based on a feedback branch having an associated longer time constant, while power usage clients with faster power response times may be provided with power budgets based on a feedback branch having an associated shorter time constant. The power budgets may be determined in the feedback branches based on power budgeting policies weighting the power budget of each subsystem relative to total power mitigation.

Coherent power management system for managing clients of varying power usage adaptability

Multi-die power synchronization

An apparatus includes a processing circuit, a power processing module, and a power management circuit. The power management circuit is configured to estimate, over time, energy consumption of the processing circuit, and to sample the estimated energy consumption using a plurality of different sampling frequencies. Each of the different sampling frequencies is used to generate a respective set of power values. The power management circuit is further configured to track a particular characteristic for each set of power values, and then to provide, for each set of power values, a particular power value that corresponds to the particular characteristic to the power processing module. Based on at least one of the particular power values, the power processing module is configured to adjust an operating parameter of the processing circuit.

Tracking power consumption using multiple sampling frequencies

Systems, methods and mechanisms for efficiently reporting sensor data of multiple processing units. In various embodiments, a computing system includes processing units and a power management unit. The processing units include multiple sensors for measuring a variety of types of sensor data. If the sensor values exceed corresponding thresholds, then a processing unit sends the sensor values to the power management unit. Logic in the power management unit stores received sensor values. When the logic determines behavior of a processing unit changes, the logic updates one or more sensor thresholds for the processing unit for changing a frequency of reporting one or more sensor values of the processing unit. The logic sends the updated one or more sensor thresholds to the processing unit. The logic updates more operating modes and operating states for the processing units based on the received sensor values.

Dashboard with push model for receiving sensor data

In an embodiment, an electronic device includes a package power zone controller. The device monitors the overall power consumption of multiple components of a 'package.' The package power zone controller may detect workloads in which the package components (e.g. different types of processors, peripheral hardware, etc.) are each consuming relatively low levels of power, but the overall power consumption is greater than a desired target. The package power zone controller may implement various mechanisms to reduce power consumption in such cases.

Package power zone for limiting power consumption even when individual consumers do not exceed individual limits

In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.

System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request

An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modern PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

Protocol neutral fabric

Methods and apparatus for integrating ARM-based IPs in computer system employing PCI-based fabrics. An PCI-based fabric is operatively coupled to an ARM-based ecosystem employing an ARM-based fabric such as OCP, AHB, or BVCI via a corresponding fabric-to-fabric bridge. Transactions between IP operatively coupled to the PCI-based fabric and IP in the ARM-based ecosystem are facilitated by applying applicable ordering and conversions operations via the fabric-to-fabric bridge and/or fabrics. For example, posted writes originating from IP coupled to the PCI-based fabric are converted to non-posted writes and serialized via the fabric-to-fabric bridge and forwarded to the ARM-based ecosystem.

Method to integrate ARM ecosystem IPs into PCI-based interconnect

An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modem PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

Growing community of inventors

Menlo Park, CA, United States of America

Achmed Rumi Zahir