Mellanox Technologies, Ltd.

Achiad Shochat

Peter Paneah

Noam Bloch

Liran Liss

Ariel Shahar

Idan Burstein

Tzahi Oved

Michael Kagan

Dror Goldenberg

Hillel Chapman

Dror Bohrer

Amir Ancel

Tamir Azarzar

Aviv Heller

Tal Gilboa

Gil Rockah

Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

Multi-socket network interface controller with consistent transaction ordering

Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.

Apparatus for communications includes a CPU, a system memory, and a network interface controller (NIC), which is configured to receive incoming data packets from a network, to post the received data packets in a designated queue for delivery to the CPU. The NIC issues interrupts to the CPU in response to the incoming data packets at a rate determined, for the designated queue, in accordance with an interrupt moderation parameter that is set for the queue. During each of a succession of monitoring periods, the CPU measures for the designated queue a current throughput of the incoming data packets and a current rate of interrupts, makes a comparison between the current measured throughput and rate of interrupts to the throughput and rate of interrupts that were measured during a preceding period in the succession, and selects and applies an update to the interrupt moderation parameter responsively to the comparison.

Dynamically-tuned interrupt moderation

A network communication device includes a host interface, which is coupled to communicate with a host processor, having a memory, so as to receive a work request to convey one or more data blocks over a network. The work request specifies a memory region of a given data size, and at least one data integrity field (DIF), having a given field size, is associated with the data blocks. Network interface circuitry is configured to execute an input/output (I/O) data transfer operation responsively to the work request so as to transfer to or from the memory a quantity of data that differs from the data size of the memory region by a multiple of the field size, while adding the at least one DIF to the transferred data or removing the at least one DIF from the transferred data.

Processing of data integrity field

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Rosh Pina, Israel

Achiad Shochat