International Business Machines Corporation

Samsung Electronics Co., Ltd.

Eidgenossische Technische Hochschule Zurich

Globalfoundries Inc.

Iowa State University Research Foundation Inc.

Hgst Netherlands, B.v.

Eth Zurich

Oxford University Innovation Ltd

University of Münster

University of Exeter

Abu Sebastian

Manuel Le Gallo-Bourdeau

Evangelos Stavros Eleftheriou

Angeliki Pantazi

Charalampos Pozidis

Tomas Tuma

Nikolaos Papandreou

Giovanni Cherubini

Wabe W Koelmans

Ghazi Sarwat Syed

Manuel Le Gallo

Vara Sudananda Prasad Jonnalagadda

Timoleon Moraitis

Irem Boybat Kara

Benedikt J Kersting

Milos Stanisavljevic

Daniel Krebs

Riduan Khaddam-Aljameh

Abbas Rahimi

Kumudu Geethan Karunaratne

Deepak Ranjan Sahoo

Lukas Kull

Alessandro Curioni

Christophe Piveteau

Luca Benini

Tuma Tomas

Michel Despont

Pier Andrea Francese

Veeresh Vidyadhar Deshpande

Walter Haeberle

Lukas Czornomaz

Konstantinos Bekas

Harish Bhaskaran

Haris Pozidis

Nandakumar Sasidharan Rajalekshmi

Vinay Manikrao Joshi

Iason Giannopoulos

Vara S P Jonnalagadda

Timothy Mathew Philip

Laurent A Dellmann

Daniele Caimi

Adelmo Cristiano Innocenza Malossi

Christophe P Rossel

Federico Zipoli

Murti V Salapaka

Martino Dazzi

Martin Salinga

Urs Frey

Reza S Moheimani

Benedikt Kersting

Athanasios Vasilopoulos

Julian Röttger Büchel

Nikolas Ioannou

Urs T Duerig

Bernd W Gotsmann

Armin W Knoll

Thomas Helmut Toifl

Jean Fompeyrine

Christoph Hermann Hagleitner

Stefan Abel

Ute Drechsler

Vinodh Venkatesan

Navaneeth Rameshan

Chiara Marchiori

Daniel Grogg

Wolfram Pernice

Rachel Cannara

Venkataraman Kartik

Peter Baechtold

Gian R Salis

Matthew Joseph Brightsky

Christopher David Wright

Nathan Youngblood

Xuan Li

Ana Stanojevic

Igor Krawczuk

Walter E M Haeberle

John Lygeros

Claudia Santini

Johannes Feldmann

Simon Haefeli

Frédéric Elias Odermatt

Urs Egger

Julian Buechel

Semiconductor devices and methods for forming the semiconductor devices are described. A semiconductor device can include a first electrode, a storage node, a second electrode and a film layer. The storage node can include phase change material deposited on top of the first electrode. The film layer can be deposited on top of the storage node and connected in a closed circuit. A voltage difference among the first electrode, the second electrode and the film layer can dictate a threshold voltage that triggers a phase change of the phase change material. An amorphous volume in the storage node can be dependent on a structural arrangement of the first electrode, the second electrode and the film layer with respect to the storage node.

Memory device with reduced threshold voltage

Photonic content-addressable memories (CAMs) and applications thereof are provided. The CAM includes a photonic cross-bar array comprising a plurality of row and column waveguides, and a plurality of photonic filter devices. Each filter device is selectively programmable in first and second states representing respective stored bit values that filters out light according to the programming. An encoder for encoding a plurality of input bit-strings into optical signals such that bit values in different bit-strings are encoded using optical signals in different pairs of optical states, and to simultaneously supply the optical signals corresponding to each bit-position in the bit-strings to a respective row waveguide of the array. The CAM further comprises a detector for detecting light in any of said optical states in each column waveguide, thereby identifying any mismatch between each input bit-string and bit values stored in the filter devices coupling light to that waveguide.

Photonic content-addressable memory and applications thereof

Systems and methods for modulating conductance of a plurality of unit cells are described. A controller can determine a plurality of conductance values for a plurality of unit cells arranged in a crossbar arrangement. The plurality of unit cells can include non-volatile memory devices. The plurality of conductance values can be less than maximum conductance values of the plurality of unit cells. The controller can determine a read gate voltage for driving a plurality of access transistors to read from connected to the plurality of unit cells under a read operation. The controller can map a plurality of weights to the plurality of conductance values and to the read gate voltage.

Conductance modulation in computational memory

The invention is directed to solving an optimization problem. The method operates a photonic crossbar array structure including N input lines and M output lines, which are interconnected at junctions via N×M photonic memory devices, where N≥2 and M≥2. The photonic memory devices are programmed to store respective weights in accordance with the optimization problem. The photonic crossbar array structure is operated as follows. First, the method determines values of L input vectors of N components each, where L≥2. Second, based on the determined values, N electromagnetic signals are generated, where each of the generated signals multiplexes L input signals encoded at respective wavelengths, so as for the N electromagnetic signals to map the L input vectors of N components each. Third, the N electromagnetic signals generated are applied to the N input lines of the photonic crossbar array structure.

Solving optimization problems with photonic crossbars

Provided is a method, device, and computer program product for programming a set of first elements onto a computational memory. The computational memory allows for performing a computation task from a set of second elements that encode the set of first elements in the computational memory, respectively. The method includes performing the computation task by the computational memory using the set of second elements and adapting at least part of the set of second elements in the computational memory based on a measured result of the computation task, until the measured result of the computation task fulfils an accuracy condition.

Programming elements onto a computational memory

The present disclosure relates to a method for compensating non-ideality of a neuromorphic memory device. The neuromorphic memory device comprising a crossbar array of wordlines and bitlines. The crossbar array comprises a block of wordline and bitline segments, wherein memory elements of the block are programmed to represent array values. The device is configured for applying a set of inputs to the initial wordlines for performing dot products. The method comprises: performing at least one of: wordline expansion or bitline expansion of the block. The set of inputs may be applied to the initial wordlines of the expanded block and in case the bitline expansion is performed an additional input may be applied to the additional wordlines of the expanded block. The currents flowing in the bitlines of the expanded block may be measured. The dot products may be determined using the measured currents.

Compensating non-ideality of a neuromorphic memory device

A memory controller circuit for mapping data of a convolutional neural network to a physical memory is disclosed. The memory controller circuit comprises a receiving unit to receive a selection parameter value, and a mapping unit to map pixel values of one layer of the convolutional neural network to memory words of the physical memory according to one of a plurality of mapping schemas, wherein the mapping is dependent on the value of the received selection parameter value.

Memory mapping of activations for convolutional neural network executions

The invention is notably directed to a method of programming memory elements of an in-memory computing (IMC) device. The IMC applies a SET signal to the K memory elements of said each cell to set each of the K memory elements to a SET state and reading K conductance values of the K memory elements in the SET state. The IMC adjusts, based on the K conductance values read and the target conductance value, a conductance value of at least one of the K memory elements to match a summed conductance of the K memory elements of said each cell with the target conductance value. The IMC maximizes a number of the K memory elements that are either in their SET state or in a RESET state of zero conductance nominal value, such that at most one of the K memory elements is neither in a SET state nor in a RESET state.

Accurate programming of analog memory devices of in-memory processing devices having a crossbar array structure

The present disclosure relates to a method for classifying a query information element using the similarity between the query information element and a set of support information elements. A resulting set of similarity scores is transformed using a sharpening function such that the transformed scores are decreasing as negative similarity scores increase and the transformed scores are increasing as positive similarity scores increase. A class of the query information element is determined based on the transformed similarity scores.

Memory-augmented neural network system

A device for performing a matrix-vector multiplication of a matrix with a vector. The device comprising a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The memory crossbar array further comprises one or more write-assist wires and one or more corresponding arrays of switching elements. The write-assist wires are connectable via the switching elements to the plurality of column lines.

Resistive memory device for matrix-vector multiplications

The invention is notably directed to a method of processing data in-memory. The method applies electrical signals to at least two input lines, which correspond to at least two rows. These two rows include at least one of the K rows and at least one of the L rows. This causes to obtain output signals in output of the M output lines, wherein the output signals depend on target values and operand values, in accordance with data stored across said at least two rows. Finally, the output signals are read out and a transformation operation is concurrently performed, in-memory, on the target values based on the operand values. This way transformed data are obtained by way of in-memory processing. The transformation may for instance be a cryptographic operation; the operand data may encode a cryptographic key. The invention is further directed to related apparatuses and systems, notably cryptographic service systems.

Processing data in-memory with memory devices having a crossbar array structure

The exemplary embodiments disclose a method, a computer program product, and a computer system for a gated recurrent neural network (RNN). The exemplary embodiments may include providing an element processor, providing a distinct memory array for a respective set of one or more elements of a hidden state vector, storing in the memory array a group of columns of weight matrices that enable a computation of the set of one or more elements, computing one or more elements of each of multiple activation vectors using a set of one or more columns of the group of columns associated with each of the multiple activation vectors, and performing by the element processor an elementwise gating operation on computed elements, resulting in the set of one or more elements.

Gated unit for a gated recurrent neural network

The present disclosure relates to a method for representing an ordered group of symbols with a hypervector. The method comprises sequentially applying on at least part of the input hypervector associated with a current symbol a predefined number of circular shift operations associated with the current symbol, resulting in a shifted hypervector. A rotate operation may be applied on the shifted hypervector, resulting in an output hypervector. If the current symbol is not the last symbol of the ordered group of symbols the output hypervector may be provided as the input hypervector associated with a subsequent symbol of the current symbol; otherwise, the output hypervector of the last symbol of the ordered group of symbols may be provided as a hypervector that represents the ordered group of symbols.

Representation of an ordered group of symbols by hypervectors

The invention is notably directed to a device comprising a plurality of resistive memory elements. The plurality of resistive memory elements comprises a resistive material. The device is configured to apply programming pulses to a subset of the plurality of resistive memory elements to perform a temporary resistance change of the resistive material of the subset for a predefined retention period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state. The device is configured such that a resistance of the subset of the plurality of resistive elements reverts automatically during the predefined retention period from the second resistance state to the first resistance state by an inherent material property of the resistive material, thereby automatically deleting the second binary state.

Device with reconfigurable short term data retention

Configurable sensor units and sensor apparatus are provided. A configurable sensor unit comprises a sensor device for generating an electrical signal, dependent on a stimulus sensed by the device, in a circuit, and a programmable non-volatile memory element operable in the circuit as a load resistor for the sensor device, whereby resistance of the load resistor depends on a programmed state of the memory element. The sensor unit has an output for providing an output signal dependent on the aforementioned electrical signal and programmed state. Sensor apparatus may comprise a plurality of these configurable sensor units. Such sensor apparatus may be configured to perform in-sensor compute operations for neural network architectures. Further sensor apparatus comprises a configurable sensor unit and a controller for programming the memory element of the sensor unit to a programmed state dependent on an operating requirement for the sensor unit.

Configurable sensor units and sensor apparatus

Growing community of inventors

Adliswil, Switzerland

Abu Sebastian