Dow Global Technolgoies LLC

Other

Abu Mokhtarul Hassan

Janusz Rajski

Robert Douglas Thompson

Nagesh Tamarapalli

Paul Aaron Gillis

Harpreet Singh

Zubin B Kuvadia

Naoko Akiya

Biplab Mukherjee

Sven Claessens

Wu Chen

Jorge H Pazmino

Dennis W Jewell

Defne Kayrak Talay

Paul A Gillis

A process for recovering monomers and solvent present in a waste stream including the steps of: (a) providing a waste feed stream containing monomers, solvent and impurities; (b) subjecting the waste feed stream of step (a) to a separation process under conditions for separating the monomers and solvent from the impurities of the waste stream; (c) recovering the monomers and solvent in one or more streams; and (d) passing the one or more of the monomer and solvent streams from step (c) to further processing.

Monomer recovery process

The present invention relates to an in situ staged steam extraction method for removing petroleum products from a heavy oil or bitumen reservoir from subterranean locations. Specifically, each injection stage comprises a different steam composition. A steam composition may consist essentially of steam or may comprise one or more enhanced oil recovery agent.

Staged steam extraction of in situ bitumen

A process includes: (a) injecting a steam composition into a subterranean location containing bitumen, the steam composition containing an alkylene glycol ether and steam, wherein the alkylene glycol ether is other than a glycol ether amine; and (b) recovering bitumen from the subterranean location to above the ground.

Enhanced steam extraction of in situ bitumen

Exemplary schemes for multi-frequency at-speed logic Built-In Self Test (BIST) are provided. For example, certain schemes allow at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. Some of the disclosed schemes are also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. In particular embodiments, the loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. In certain embodiments, only the capture cycle is performed at the corresponding system timing. In some embodiments, a programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.

Method and apparatus for at-speed testing of digital circuits

A scheme for multi-frequency at-speed logic Built-In Self Test (BIST) is provided. This scheme allows at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. The scheme is also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. Scanable memory elements of the digital circuit are connected to define plurality of scan chains. The loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. The BIST controller, Pseudo-Random Pattern Generator (PRPG) and Multi-input Signature Register (MISR) work at slower frequency than the fastest clock domain. After loading of a new test pattern, a clock suppression circuit allows a scan enable signal to propagate for more that one clock cycle before multiple capture clock is applied. This feature relaxes the speed and skew constraints on scan enable signal design. Only the capture cycle is performed at the corresponding system timing. A programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.

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Pearland, TX, United States of America

Abu Mokhtarul Hassan